Results 71 to 80 of about 248 (147)

Increasing energy efficiency and instruction scheduling by software prefetching

, 2016
Alexander Fougner
openalex   +1 more source

Decoding non-random mutational signatures at Cas9 targeted sites. [PDF]

Nucleic Acids Res, 2018
Taheri-Ghahfarokhi A, Taylor BJM, Nitsch R, Lundin A, Cavallo AL, Madeyski-Bengtson K, Karlsson F, Clausen M, Hicks R, Mayr LM, Bohlooly-Y M, Maresca M.   +11 more
europepmc   +1 more source

Solving global shallow water equations on heterogeneous supercomputers. [PDF]

PLoS One, 2017
Fu H, Gan L, Yang C, Xue W, Wang L, Wang X, Huang X, Yang G.   +7 more
europepmc   +1 more source

Information systems integration in radiology. [PDF]

J Digit Imaging, 1999
Honeyman JC.
europepmc   +1 more source

Instruction prefetch strategies in a pipelined processor

, 1983
Hubert R. McLellan
openalex   +1 more source

Understanding GPU Programming for Statistical Computation: Studies in Massively Parallel Massive Mixtures. [PDF]

J Comput Graph Stat, 2010
Suchard MA, Wang Q, Chan C, Frelinger J, Cron A, West M.   +5 more
europepmc   +1 more source

Evaluation of Instruction Prefetch Methods for Coresonic DSP Processor

, 2016
Tobias Lind
openalex   +1 more source

Pancreatic islet cell tumour demonstrated by aortography. [PDF]

Proc R Soc Med, 1968
Birnstingl MA, Leggett HA.
europepmc   +1 more source

Non-referenced prefetch (NRP) cache for instruction prefetching

IEE Proceedings - Computers and Digital Techniques, 1996
A new conceptual cache, NRP (nonreferenced prefetch) cache, is proposed to improve the performance of instruction prefetch mechanisms which try to prefetch both the sequential and nonsequential blocks under limited memory bandwidth. The NRP cache is used for storing prefetched blocks that were not referenced by the CPU.
G.-H. Park, Oh‐Young Kwon, Tengfei Han, S. Kim   +3 more
openalex   +2 more sources

Branch history guided instruction prefetching

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2002
Instruction cache misses stall the fetch stage of the processor pipeline and hence affect instruction supply to the processor. Instruction prefetching has been proposed as a mechanism to reduce instruction cache (I-cache) misses. However, a prefetch is effective only if accurate and initiated sufficiently early to cover the miss penalty.
V. Prasanna Srinivasan, Edward S. Davidson, Gary Tyson, Mary Jay Charney, Thomas R. Puzak   +4 more
openalex   +2 more sources