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Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020 Hardware prefetching is one of the common off-chip DRAM latency hiding techniques. Though hardware prefetchers are ubiquitous in the commercial machines and prefetching techniques are well studied in the computer architecture community, the "memory wall" problem still exists after decades of micro-architecture research and is considered to be an ...
Samuel Pakalapati, Biswabandan Panda
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WCET analysis of instruction caches with prefetching
ACM SIGPLAN Notices, 2007 Instruction prefetching is an effective technique to reduce the instruction cache miss latency for improving the average-case performance. For real-time systems, however, the use of instruction prefetching will only besuitable if a reasonably tight worst-case performance of programs using instruction prefetching can be predicted. This paper presents an
Jun Yan, Wei Zhang
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Architectural and compiler support for effective instruction prefetching
ACM Transactions on Computer Systems, 2001 Instruction cache miss latency is becoming an increasingly important performance bottleneck, especially for commercial applications. Although instruction prefetching is an attractive technique for tolerating this latency, we find that existing prefetching schemes are insufficient for modern superscalar processors, since they fail to issue prefetches ...
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Threaded prefetching: An adaptive instruction prefetch mechanism
Microprocessing and Microprogramming, 1993Abstract We propose and analyze an adaptive instruction prefetch scheme, called threaded prefetching, that makes use of history information to guide the prefetching. The scheme is based on the observation that control flow paths are likely to repeat themselves.
Seong Baeg Kim +6 more
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Prefetching in supercomputer instruction caches
Proceedings Supercomputing '92, 2003Prefetching methods for instruction caches in supercomputers are studied via trace-driven simulation. The two primary methods studied are fall-through prefetch for sequential line accesses and target prefetch for nonsequential ones. As measured by miss rate, both methods are shown to improve performance significantly.
J.E. Smith, W.-C. Hsu
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An improved lookahead instruction prefetching
Proceedings High Performance Computing on the Information Superhighway. HPC Asia '97, 2002A new lookahead instruction prefetching mechanism is proposed in this paper. Though significant performance improvement can be obtained by improving both the cache miss ratio and average access time for successfully prefetched blocks, most conventional prefetching mechanisms improve only one out of the two factors.
null Gi-Ho Park +4 more
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Rebasing Instruction Prefetching: An Industry Perspective
IEEE Computer Architecture Letters, 2020Instruction prefetching can play a pivotal role in improving the performance of workloads with large instruction footprints and frequent, costly frontend stalls. In particular, Fetch Directed Prefetching (FDP) is an effective technique to mitigate frontend stalls since it leverages existing branch prediction resources in a processor and incurs very ...
Yasuo Ishii +3 more
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Instruction prefetching using Basicblock prediction
2008 International Conference on Electronic Design, 2008Memory latency is a significant bottleneck in modern computer architectures, especially for commercial and multimedia applications. Instruction cache misses can severely limit the performance, due to advent of superscalar processors and multicore systems.
K. Shyamala +4 more
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Instruction cache prefetching with extended BTB
Proceedings 1997 International Conference on Parallel and Distributed Systems, 2002Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determine the target line to be prefetched based on the current fetched line address. However, as the cache line becomes wider, there may be multiple branches in a cache line which hurdles the decision made by these ...
null Shuh-An Chi +4 more
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