Results 51 to 60 of about 9,050,905 (317)

Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration [PDF]

Jisuanji gongcheng
Currently, dynamic refactoring is implemented by configuring it through on-chip interfaces, usually using the dynamic refactoring control Intellectual Property (IP) core provided by the official Field Programmable Gate Array (FPGA), and connected to the ...
ZHOU Xuanjin, CAI Gang, HUANG Zhihong
doaj   +1 more source

Pediatric Oncology Nursing Competencies in Latin America and the Caribbean: A Scoping Review to Inform Practice, Education, and Research

Pediatric Blood &Cancer, EarlyView.
ABSTRACT Background Nurses are central to cancer care for children and adolescents, yet no comprehensive synthesis has defined essential core competencies for pediatric oncology nursing (PON) practice internationally, particularly in Latin America and the Caribbean (LAC).
Luís Carlos Lopes‐Júnior, Edmara Bazoni Soares Maia, Soad Fuentes‐Alabí, Courtney E. Sullivan, Monnie Abraham, Mauricio Maza, Liliana Vásquez Ponce, Regina Aparecida Garcia Lima   +7 more
wiley   +1 more source

A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

International Journal of Antennas and Propagation, 2012
We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set.
Dau-Chyrh Chang, Lihong Zhang, Xiaoling Yang, Shao-Hsiang Yen, Wenhua Yu   +4 more
doaj   +1 more source

Comprehensive Review of Research on Dynamic Binary Translation Techniques [PDF]

Jisuanji kexue yu tansuo
Solving compatibility issues in programs is crucial for building a domestic software ecosystem. With the diversification of computer architectures, ensuring software runs smoothly across different platforms and hardware environments has become an urgent ...
ZHANG Jin, SHAN Zehu, LIU Xiaodong, WANG Wenzhu, YU Jie, PENG Long, XIE Qiyou
doaj   +1 more source

Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection

IEEE Access, 2022
This paper describes the design and implementation of a driver drowsiness detection (DDD) system using a modified RiscV processor on a field-programmable gate array (FPGA).
Seyed Kian Mousavikia, Erfan Gholizadehazari, Morteza Mousazadeh, Siddika Berna Ors Yalcin   +3 more
doaj   +1 more source

Performance Debugging and Tuning using an Instruction-Set Simulator [PDF]

, 1997
Instruction-set simulators allow programmers a detailed level of insight into, and control over, the execution of a program, including parallel programs and operating systems.
Magnusson, Peter S., Montelius, Johan
core   +3 more sources

Straight-line instruction sequence completeness for total calculation on cancellation meadows [PDF]

, 2009
A combination of program algebra with the theory of meadows is designed leading to a theory of computation in algebraic structures which use in addition to a zero test and copying instructions the instruction set $\{x \Leftarrow 0, x \Leftarrow 1, x ...
Bergstra, Jan A., Bethke, Inge
core   +2 more sources

Prevalence and Trajectory of Household Material Hardship Among Children With Advanced Cancer

Pediatric Blood &Cancer, EarlyView.
ABSTRACT Background/Objectives Families of children with advanced cancer living in poverty experience inferior outcomes including poor parent mental health and worse child quality of life. Household material hardship (HMH: food, housing, transportation, and/or utility insecurity) is a modifiable poverty exposure—and potential intervention target—that ...
Sarah Wright, Morgan A. Paul, Selena Murcia Mendez, Emily Jones, Lucille Lokko, Chelsea Heneghan, Nicholas Purol, Morgan Arnold, Rahela Aziz‐Bose, Colleen A. Kelly, Sandi L. Pruitt, Joanne Wolfe, Kira Bona, Puja J. Umaretiya   +13 more
wiley   +1 more source

Neural Network Acceleration Architecture Based on RISC-V Instruction Set Extension [PDF]

Jisuanji kexue
To address the current shortcomings of RISC-V-based neural network accelerators in accelerating matrix computations and nonlinear operations within Transformer-based models,a neural network acceleration architecture based on RISC-V instruction set ...
CAI Chenghuan, WANG Yipin, XU Jiabin, ZHANG Fengzhe, ZHOU Xuegong, CAO Wei, ZHANG Fan, YU Xinsheng
doaj   +1 more source

Compiling Optimization Method of Address Immediate Value Based on C-SKY CPU [PDF]

Jisuanji gongcheng, 2016
As Reduced Instruction Set Computer(RISC) architecture processors generally use fixed-length instructions,they have to perform the function of long jump instruction in Complex Instruction Set Computer(CISC) architecture processors by a literal pool.This ...
LIAN Yulong,SHI Zheng,LI Chunqiang,WANG Huibin,SHANG Yunhai
doaj   +1 more source