Results 251 to 260 of about 192,536 (344)
Some of the next articles are maybe not open access.
Hard X-ray free-electron laser with femtosecond-scale timing jitter
Nature Photonics, 2017Heung-Sik Kang +2 more
exaly +2 more sources
A 20-GHz PLL With 20.9-fs Random Jitter
IEEE Journal of Solid-State Circuits, 2023This article describes an integer- $N$ phase-locked loop (PLL) that incorporates a phase detector sampling both the rising and falling edges of the reference clock. The circuit also uses a new retiming method in the feedback divider.
Yu Zhao, M. Forghani, Behzad Razavi
semanticscholar +1 more source
IEEE Journal of Solid-State Circuits, 2021
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture.
Wanghua Wu +8 more
semanticscholar +1 more source
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture.
Wanghua Wu +8 more
semanticscholar +1 more source
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
IEEE Journal of Solid-State Circuits, 2022This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which ...
M. Mercandelli +7 more
semanticscholar +1 more source
IEEE International Solid-State Circuits Conference, 2022
With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers.
Xinlin Geng +5 more
semanticscholar +1 more source
With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers.
Xinlin Geng +5 more
semanticscholar +1 more source
Jitter-Power Trade-Offs in PLLs
IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2021As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe ...
B. Razavi
semanticscholar +1 more source
Single fiber electromyography and measuring jitter with concentric needle electrodes
Muscle and Nerve, 2022This monograph contains descriptions of the single fiber electromyography (SFEMG) method and of the more recently implemented method of recording jitter with concentric needle electrodes (CNEs).
D. Sanders +2 more
semanticscholar +1 more source
Journal of optical communications, 2021
This study has simulated the raised cosine, linear, cubic measured pulses numerically with electrical jitter amplitude variations impact on fiber communication systems.
Mahmoud M. A. Eid +4 more
semanticscholar +1 more source
This study has simulated the raised cosine, linear, cubic measured pulses numerically with electrical jitter amplitude variations impact on fiber communication systems.
Mahmoud M. A. Eid +4 more
semanticscholar +1 more source
IEEE Transactions on Vehicular Technology, 2021
Flexible mobility and random jitter are two unique features of UAV communication platforms. Although advantages of mobility have been extensively explored, the random jitter of UAV platforms, caused by airflow and body vibrations, has been rarely studied.
Huici Wu +4 more
semanticscholar +1 more source
Flexible mobility and random jitter are two unique features of UAV communication platforms. Although advantages of mobility have been extensively explored, the random jitter of UAV platforms, caused by airflow and body vibrations, has been rarely studied.
Huici Wu +4 more
semanticscholar +1 more source

