Results 261 to 270 of about 192,536 (344)
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The jitter measurement ways: The jitter decomposition
IEEE Instrumentation & Measurement Magazine, 2020Today, several applications and technologies require a suitable jitter characterization. For this reason, measurement methods and instruments aimed at quantifying and analyzing jitter continue to be proposed and developed by the research community and manufacturers.
Balestrieri E. +5 more
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IEEE Journal of Solid-State Circuits, 2020
This article presents a fractional- ${N}$ frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops.
Alessio Santiccioli +7 more
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This article presents a fractional- ${N}$ frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops.
Alessio Santiccioli +7 more
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A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM
IEEE Journal of Solid-State Circuits, 2020This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of limited output voltage range of LV charge pump (CP).
Zhao Zhang, Guang Zhu
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Phase jitter/spl equiv/timing jitter?
IEEE Communications Letters, 1998In digital communication systems, the periodicity of timing signals is often disturbed. While timing jitter has been adopted by the International Telecommunication Union (ITU) as the standardized measurement for such disturbances, phase jitter is often used instead in much of the current relevant literature.
J. Chin, A. Cantoni
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The jitter measurement ways: The jitter graphs
IEEE Instrumentation & Measurement Magazine, 2019In recent years, jitter characterization has acquired an ever greater importance for many applications and standard technologies. As a consequence, several measurement approaches have been developed, including different jitter graphical representations, decomposition methods and measurement instruments that can be used singularly or together ...
Eulalia Balestrieri +3 more
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Enhanced Resolution Jitter Testing Using Jitter Expansion
25th IEEE VLSI Test Symmposium (VTS'07), 2007This paper presents a hardware jitter expansion technique to enable high-resolution jitter measurement of multi-GHz digital signals. To realize high-resolution timing analysis, the jitter is reconstructed on a low-speed signal and jitter measurements are made on this signal instead of the original high-speed signal.
Hyun Choi +2 more
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Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division
Journal of Electronic Testing, 2003This paper presents a new method for measuring random timing jitter or sinusoidal timing jitter in signals of telecommunication devices. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter.
Takahiro J. Yamaguchi +4 more
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Adaptive Hybrid Beamforming for UAV mmWave Communications Against Asymmetric Jitter
IEEE Transactions on Wireless CommunicationsJittering effect is a critical issue in the unmanned aerial vehicle (UAV) millimeter wave (mmWave) communications. In this paper, we identify and characterize the asymmetric impact of jitter on the angular domain information in the UAV mmWave channels ...
Wenyun Chen +4 more
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IEEE International Solid-State Circuits Conference, 2019
Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25 GHz) can effectively suppress the integrated jitter
Zunsong Yang +4 more
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Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25 GHz) can effectively suppress the integrated jitter
Zunsong Yang +4 more
semanticscholar +1 more source
A Review on Power Supply Induced Jitter
IEEE Transactions on Components, Packaging, and Manufacturing Technology, 2019The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the ...
J. N. Tripathi, V. Sharma, H. Shrimali
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