Results 21 to 30 of about 192,536 (344)
IEEE Access, 2023 Beyond 5th generation (5G) and 6th generation (6G) mobile systems require not only low latency but also low jitter for deterministic services such as remote operation.
Kenji Miyamoto +3 more
doaj +1 more source
Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs [PDF]
, 2002 This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume
Beek, Remco C.H. van de +3 more
core +2 more sources
Femtosecond Relativistic Electron Beam with Reduced Timing Jitter from THz Driven Beam Compression. [PDF]
Physical Review Letters, 2019 We propose and demonstrate a method to reduce the pulse width and timing jitter of a relativistic electron beam through THz driven beam compression. In this method the longitudinal phase space of a relativistic electron beam is manipulated by a linearly ...
Lingrong Zhao +12 more
semanticscholar +1 more source
Understanding stellar activity-induced radial velocity jitter using simultaneous K2 photometry and HARPS RV measurements [PDF]
, 2017 One of the best ways to improve our understanding of the stellar activity-induced signal in radial velocity (RV) measurements is through simultaneous high-precision photometric and RV observations.
Adibekyan, V. +17 more
core +3 more sources
Development of a tool to objectively identify normal human voice
BLDE University Journal of Health Sciences, 2020 Acoustic analysis is used to assist differential diagnosis, documentation and evaluation of treatment for voice disorders. Clinical data has shown that Jitter, Shimmer, Mean Pitch and Harmonic Noise Ratio are the indices of voice pathology.
H T Lathadevi, S P Guggarigoudar
doaj +1 more source
Jitter Limitations on Multi-Carrier Modulation [PDF]
, 2005 A feasibility study is made of an OFDM system based on analog multipliers and integrate-and-dump blocks, targeted at Gb/s copper interconnects. The effective amplitude variation of the integrator output caused by jitter is explained in an intuitive way ...
Klumperink, E.A.M. +3 more
core +2 more sources
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops [PDF]
, 2009 This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL.
Gao, X. +3 more
core +2 more sources
Workshop on Cryptographic Hardware and Embedded Systems, 2017 In the context of the security evaluation of cryptographic implementations, profiling attacks (aka Template Attacks) play a fundamental role. Nowadays the most popular Template Attack strategy consists in approximating the information leakages by ...
Eleonora Cagli +2 more
semanticscholar +1 more source
Binary phase detector gain in bang-bang phase-locked loops with DCO jitter [PDF]
, 2010 Bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear ...
Budiharti, R. (Rini) +3 more
core +3 more sources