Results 31 to 40 of about 513,175 (343)

Surface morphology of polyimide thin film dip-coated on polyester filament for dielectric layer in fibrous organic field effect transistor [PDF]

, 2014
The idea of wearable electronics automatically leads to the concept of integrating electronic functions on textile substrates. Since this substrate type implies certain challenges in comparison with their rigid electronic companions, it is of utmost ...
Bruneel, Els, Rambausek, Lina, Van Driessche, Isabel, Van Langenhove, Lieva   +3 more
core   +1 more source

InGaAs/InP double heterostructures on InP/Si templates fabricated by wafer bonding and hydrogen-induced exfoliation [PDF]

, 2003
Hydrogen-induced exfoliation combined with wafer bonding has been used to transfer ~600-nm-thick films of (100) InP to Si substrates. Cross-section transmission electron microscopy (TEM) shows a transferred crystalline InP layer with no observable ...
Ahrenkiel, S. P., Atwater, Harry A., Fontcuberta i Morral, A., Wanlass, M. W., Zahler, J. M.   +4 more
core   +1 more source

High Dielectric Breakdown Strength Nanoplatelet‐Based Multilayer Thin Films

Macromolecular Materials and Engineering, 2023
Dielectric materials that can withstand high voltages are of great interest due to the growing need for high‐performance insulation systems in electronics. Polymer nanocomposites have gained popularity as electrical insulators due to their processability,
Bethany Palen, Ethan T. Iverson, Matthew G. Rabaey, Shaik Merkatur Hakim Marjuban, Carolyn T. Long, Thomas J. Kolibaba, Annie Benson, Homero Castaneda‐Lopez, Jaime C. Grunlan   +8 more
doaj   +1 more source

Ion traps fabricated in a CMOS foundry [PDF]

, 2014
We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes.
A. M. Eltony, C. D. Bruzewicz, Chiaverini J., I. L. Chuang, J. Chiaverini, J. M. Sage, K. K. Mehta, Leibrandt D., R. J. Ram   +8 more
core   +2 more sources

Flexible three-dimensional artificial synapse networks with correlated learning and trainable memory capability

Nature Communications, 2017
High-density information storage calls for the development of modern electronics with multiple stacking architectures that increase the complexity of three-dimensional interconnectivity. Here, Wu et al.
Chaoxing Wu, Tae Whan Kim, Hwan Young Choi, Dmitri B. Strukov, J. Joshua Yang   +4 more
doaj   +1 more source

Graphene field-effect-transistors with high on/off current ratio and large transport band gap at room temperature

, 2010
Graphene is considered to be a promising candidate for future nano-electronics due to its exceptional electronic properties. Unfortunately, the graphene field-effect-transistors (FETs) cannot be turned off effectively due to the absence of a bandgap ...
Appenzeller J., Castro E. V., Chen Z., Farmer D. B., Han M. Y., Li X., Mak K. F., McCann E., Min H., Ni Z. H., Novoselov K. S., Novoselov K. S., Ohta T., Oostinga J. B., Pereira V. M., Ritter K. A., Ryzhii V., San-Jose P., Sze S. M., Tonouchi M., Wang F., Wang X., Xia F., Zhang Y., Zhang Y., Zhou S. Y.   +25 more
core   +1 more source

Flexible supercapacitor electrodes based on real metal-like cellulose papers

Nature Communications, 2017
With ligand-mediated layer-by-layer assembly between metal nanoparticles and small organic molecules, the authors prepare metallic paper electrodes for supercapacitors with high power and energy densities.
Yongmin Ko, Minseong Kwon, Wan Ki Bae, Byeongyong Lee, Seung Woo Lee, Jinhan Cho   +5 more
doaj   +1 more source

Monolithic Pixel Sensors in Deep-Submicron SOI Technology

, 2009
Monolithic pixel sensors for charged particle detection and imaging applications have been designed and fabricated using commercially available, deep-submicron Silicon-On-Insulator (SOI) processes, which insulate a thin layer of integrated full CMOS ...
, C Q Vu, D Bisello, D Contarato, F. Gaede ., L Glesener, M Battaglia, P Denes, P Giubilato, P. Giubilato ., R. Brun, S Mattiazzo   +11 more
core   +1 more source

The Layer 0 Inner Silicon Detector of the D0 Experiment

, 2009
This paper describes the design, fabrication, installation and performance of the new inner layer called Layer 0 (L0) that was inserted in the existing Run IIa Silicon Micro-Strip Tracker (SMT) of the D0 experiment at the Fermilab Tevatron collider.
A. Bean, A. Nomerotski, A. Zieminski, C.E. Gerber, C.H. Daly, Cooper, D. Buchholz, D. Butler, D. Markley, D. Olis, D. Strom, D. Tsybychev, E. Shabalina, F. Lehner, G.J. Otero y Garzón, Garcia-Sciveres, H. Gonzalez, H. Guldenman, H.J. Lubatti, J. Foglesong, J. Green, J. Howell, J. Wang, K. Hanagaki, K. Herner, K. Krempetz, K. Schultz, Krieger, L. Bagby, L. Christofek, Lutz, M. Demarteau, M. Hrycyk, M. Johnson, M. Kirby, M. Matulik, M. Roman, M. Tuttle, M. Utes, M. Weber, R. Angstadt, R. Lipton, R. Rucinski, R.D. Taylor, R.L. McCarthy, R.P. Smith, S.W. Youn, T. Bolton, T. Wesson, T. Zhou, W. Kuykendall, W.E. Cooper, Y. Orlov, Zimmerman, Zimmerman   +54 more
core   +1 more source

Electrical Control of Silicon Photonic Crystal Cavity by Graphene [PDF]

, 2012
Efficient conversion of electrical signal to optical signal in nano-photonics enables solid state integration of electronics and photonics. Combination of graphene with photonic crystals is promising for electro-optic modulation.
Kim, Jonghwan, Majumdar, Arka, Vuckovic, Jelena, Wang, Feng   +3 more
core   +1 more source