Results 121 to 130 of about 12,374 (228)
, 2005 A recently proposed space-time signal construction method that combines orthogonal design with sphere packing, referred to here as (STBC-SP), has shown useful performance improvements over Alamouti’s conventional orthogonal design.
Alamri, O.R. +3 more
core
Differentially Encoded LDPC Codes—Part II: General Case and Code Optimization
EURASIP Journal on Wireless Communications and Networking, 2008 This two-part series of papers studies the theory and practice of differentially encoded low-density parity-check (DE-LDPC) codes, especially in the context of noncoherent detection.
Li (Tiffany) Jing
doaj
A Turbo-Detection Aided Serially Concatenated MPEG-4/TCM Videophone Transceiver
, 2004 A Turbo-detection aided serially concatenated inner Trellis Coded Modulation (TCM) scheme is combined with four different outer codes, namely with a Reversible Variable Length Code (RVLC), a Non-Systematic Convolutional (NSC) code a Recursive Systematic ...
Ng, S. X. +3 more
core
, 2012 The aim of this thesis are problematics about LDPC codes. There are described metods to create parity check matrix, where are important structured metods using finite geometry: Euclidean geometry and projectice geometry.
Hrouza, Ondřej
core
Hardware-Aware GA-Based Regular Quasi-Cyclic LDPC Code Search Algorithm
, 2007 Gallager’s Low-Density Parity-Check (LDPC) codes have recently received a lot of attention because of their excellent performance and low decoding complexity.
黎煥昇, Li, Huan-Sheng
core
Scalable High HUE LDPC Decoder Architecture Design
, 2007 Low-density parity check (LDPC) codes have been shown that it is a strong competitor of Turbo codes. LDPC codes offer excellent coding gain and provide elegant low computation complexity when comparing with Turbo codes. The complex routing nature of LDPC
簡義興, Chien, Yi-hsing
core
Network-on-Chip Optimization: as shown through a novel LDPC Decoder Design
, 2010 In this work we describe the network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power ...
Mineo, Christopher Alexander
core
RL-Based Parallel LDPC Decoding with Clustered Scheduling. [PDF]
Entropy (Basel)Ozkan Y, Yakimenka Y, Kliewer J.
europepmc +1 more source
VLSI Designs of LDPC Codec for IEEE 802.16e System
, 2007 在新一代IEEE 802.16e標準的無線通訊系統中，除提供定點通訊的操作模式外，更增加有限的可移動性，尤其是在車速移動下進行高速率資料傳輸和提供語音功能。除此，其特色是能涵蓋更遠的傳輸距離、提供更大的頻寬，以及提升頻帶使用率。為了增加傳輸的可靠性，低密度奇偶校驗編碼(low-density parity-check, LDPC)成為IEEE 802.16e標準中極為重要通道編碼(channel coding)的模組，提供更強大的錯誤更正能力。 低密度奇偶校驗編碼最早是由Robert ...
施信毓, Shi, Xin-Yu
core