Results 1 to 10 of about 112,170 (164)
Active Leakage Power Optimization for FPGAs [PDF]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006 Active leakage power dissipation is considered in field-programmable gate arrays (FPGAs) and two "no cost" approaches for active leakage reduction are presented. It is well known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs.
F N Najm
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Dynamic Power Consumption and Delay Analysis for Ultra-Low Power 2 to 1 Multiplexer Designs
Advances in Electrical and Electronic Engineering, 2021 This paper highlights a comparative analysis of eight diverse techniques for 2 to 1 multiplexer implementation. The functionality is identical but significant differences in dynamic power consumption and propagation delay are observed. This paper aims to
Nishant Kumar +3 more
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Power Prediction in Register Files Using Machine Learning
IEEE Access, 2022 The advent of computer architecture and processor design in recent years has brought about the need to design larger register files that can hold more instructions and operands to support faster processors.
Mohammed Elnawawy +2 more
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Design of 7T SRAM Using InGaAs-Dual Pocket-Dual Gate-Tunnel FET for IoT Applications
IEEE Access, 2023 The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical devices, and home automation systems.
Gadarapulla Rasheed +1 more
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A Power Efficient Based DC to DC Converter Using SCC
EAI Endorsed Transactions on Energy Web, 2021 Scaling is one of the most important aspects and is considered for designing digital circuits. With the help of scaling techniques, it can integrate more features into the chip for optimization of actual circuit space.
S. Anusooya, P. K. Jawahar
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A Novel Cross-Latch Shift Register Scheme for Low Power Applications
Applied Sciences, 2020 The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying
Po-Yu Kuo +4 more
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On the Limits of Leakage Power Reduction in Caches [PDF]
11th International Symposium on High-Performance Computer Architecture, 2005 If current technology scaling trends hold, leakage power dissipation soon becomes the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage problem. While there has been a flurry of research in this area
Yan Meng, Timothy Sherwood, Ryan Kastner
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Zhongguo dianli, 2022 In order to improve the security of power grid information, an anti leakage technology of power grid information based on service call authentication login interface is proposed.
Danhui LAI +4 more
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Active leakage power optimization for FPGAs [PDF]
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, 2004 We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-tables) that ...
Jason Helge Anderson +2 more
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Application of cross-hole electrical method to detection of the hidden leakage of diaphragm walls
Yantu gongcheng xuebao, 2023 In order to locate the hidden leakage of underground diaphragm walls, the numerical simulation studies on the detection of leakage defects of underground diaphragm walls are carried out by using the cross-hole quadrupole method and the tripole method ...
CHEN Liang 1, 2, YAN Shufa 1, 2, WAN Yu 1, 2
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