Results 1 to 10 of about 5,016,217 (299)
Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop [PDF]
Micromachines, 2019 An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage ...
Jaeyoung Park, Young Uk Yim
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Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing [PDF]
IEEE Access, 2021 Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications.
Zeinab Seifoori +2 more
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Power gating strategies on GPUs [PDF]
ACM Transactions on Architecture and Code Optimization, 2011 As technology continues to shrink, reducing leakage is critical to achieving energy efficiency. Previous studies on low-power GPUs (Graphics Processing Units) focused on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage and Frequency Scaling) and clock gating.
Po-Han Wang 0001 +3 more
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A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design
Iraqi Journal of Industrial Research, 2022 Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design.
Ahmed Lateef Hameed +2 more
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Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time [PDF]
EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, 2018 The power gating is one of the most popular reduction leakage techniques. We make comparison among various power gating schemes in terms of power delay product, energy loss, and wake-up time using the 45-nm Predictive Technology Model.
Minh Vo
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A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds
Journal of Low Power Electronics and Applications, 2023 The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access ...
Yujin Zheng, Alex Yakovlev, Alex Bystrov
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A New Physical Design Flow for a Selective State Retention Based Approach
Journal of Low Power Electronics and Applications, 2021 This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design.
Joseph Rabinowicz, Shlomo Greenberg
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IEEE Open Journal of Circuits and Systems, 2021 An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications.
Hayato Yoshida +4 more
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A Dynamic Instrumentation Amplifier for Low-Power and Low-Noise Biopotential Acquisition
Sensors, 2016 A low-power and low-noise dynamic instrumentation amplifier (IA) for biopotential acquisition is presented. A dynamic IA that can reduce power consumption with a timely piecewise power-gating method, and noise level with an alternating input and chopper ...
Jongpal Kim, Hyoungho Ko
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Sensors, 2021 The goal of this paper is to present a compact low-cost and low-power prototype of a pulsed Ultra Wide Band (UWB) oscillator and an UWB elliptical dipole antenna integrated on the same Radio Frequency (RF) Printed Circuit Board (PCB) and its digital ...
Stefano Bottigliero, Riccardo Maggiora
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