Results 21 to 30 of about 5,016,217 (299)

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Journal of Electrical and Computer Engineering, 2015
Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating
Feng Wang, Xiantuo Tang, Zuocheng Xing
doaj   +1 more source

CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer

Walailak Journal of Science and Technology, 2016
Clock gating is an effective technique of decreasing dynamic power dissipation in synchronous design. One of the methods used to realize this goal is to mask the clock which goes to the unnecessary to use in specific time.
Maan HAMEED, Asem KHMAG, Fakhrul ZAMAN, Abdurrahman RAMLI   +3 more
doaj   +1 more source

Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs [PDF]

Electronics, 2016
An independent-gate FinFET can operate in two modes: SG (shorted-gate) and IG (independent-gate) modes, and thus a FinFET-based circuit offers rich design options for lower power, better performance or reduced transistor count.
Meng-Chou Chang, Kai-Lun He, Yu-Chieh Wang   +2 more
doaj   +1 more source

Delay test for diagnosis of power switches [PDF]

, 2014
Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosingpower switches.
Shi, Kan, Wilson, Peter R., Chakrabarty, Krishnendu, Krishnendu Chakrabarty, Al-Hashimi, Bashir, Peter R. Wilson, Khursheed, Syed Saqib, Bashir M. Al-Hashimi, Kan Shi, Saqib Khursheed, Wilson, Peter R, Al-Hashimi, Bashir M, Khursheed, Saqib   +12 more
core   +1 more source

Gate sizing for low power design [PDF]

, 2002
Low power design based on minimal size gate implementation induces great speed penalty. We present a new gate sizing method for improving the speed performance of static logic paths designed in submicron CMOS technologies without increasing the power dissipation obtained with a minimal surface implantation.
Maurine, Philippe, Azemard, Nadine, Auvergne, Daniel   +2 more
openaire   +3 more sources

Power Gating Implentation for Low Power Optimizations using Gates

, 2023
Modern days need modern solutions, with the urge in the demand to lower the dissipated power. The integrated circuits with low power VLSI applications prefer a circuit design offer low power while in sleep without any performance degradation. One way to reduce the dissipated power is by using power gating.
openaire   +2 more sources

Glitch-Free Clock Distribution Using Flip-Flop–Controlled Clock Gating in a 32-Bit RISC-V Architecture

ITEGAM-JETIA
Clock distribution contributes significantly to the dynamic power consumption of contemporary embedded processors, especially in low-power 32-bit RISC-V cores.
Himabindhu Jala, Karimullah Shaik
doaj   +1 more source

Theoretical implication of liganding reactions in axonal sodium channel gating [PDF]

, 1980
Dorogi PL, Neumann E. Theoretical implication of liganding reactions in axonal sodium channel gating. Neurochemistry International. 1980;2:45-51.Mathematical simulation models for measured permeability properties of axonal Na+ channels point to the ...
Dorogi, Peter L., Neumann, Eberhard
core   +1 more source

Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications

Sensors, 2023
A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD).
Christoph Ribisch, Michael Hofbauer, Seyed Saman Kohneh Poushi, Alexander Zimmer, Kerstin Schneider-Hornstein, Bernhard Goll, Horst Zimmermann   +6 more
doaj   +1 more source

VLSI Synthesis for Low-Power Clocking in Synchronous Designs

Iraqi Journal of Industrial Research
In the field of information theory, the significance of low-power techniques cannot be overstated. Among these, clock gating stands out as a potent method to mitigate power dissipation in synchronous designs.
Naseer Alwan Hussein, Maan Hameed, Luay Ali Khamees   +2 more
doaj   +1 more source