Results 151 to 160 of about 439,988 (198)

Leakage Power: Challenges and Solutions

2003
The steady down-scaling of CMOS device dimensions has been the main stimulus for the growth of microelectronics and the computer industry over the last three decades. Without down-scaling, the recent proliferation of mobile devices such as portable phones and personal computers, and the tremendous performance of workstations could not have been ...
Mohab Anis, Mohamed Elmasry
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CMOS leakage power at cell level

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., 2006
Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level.
R. Mendoza, A. Ferre, L. Balado, J. Figueras   +3 more
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Sleepy Stack Reduction of Leakage Power

2004
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design.
Jun Cheol Park, Vincent J. Mooney, Philipp Pfeiffenberger   +2 more
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LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES

Journal of Circuits, Systems and Computers, 2011
With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. A dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications.
BEHNAM GHAVAMI, HOSSEIN PEDRAM, AREZOO SALARPOUR   +2 more
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Leakage power optimization in standard-cell designs

Proceedings of the 17th symposium on Integrated circuits and system design, 2004
Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90nm), sub-threshold leakage currents are still dominant with respect to gate currents ...
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Leakage power-aware clock skew scheduling

Proceedings of the 45th annual Design Automation Conference, 2008
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and ...
Min Ni, Seda Ogrenci Memik
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Techniques for Leakage Power Reduction

2009
This chapter contains sections titled: Introduction Transistor Leakage Current Components Circuit Subthreshold Leakage Current Leakage Control Techniques This chapter contains sections titled: Acknowledgments ...
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Process Variation and Leakage Power

2011
Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large Process Variation (PV).
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Innovative power gating for leakage reduction

2008 IEEE International Symposium on Circuits and Systems, 2008
Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-F/A reduced power gating structure is proposed for better reduction of leakage currents, especially ...
Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled   +2 more
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Traditional Statistical Leakage Power Analysis Methods

2012
Process-induced variability has huge impact on the circuit performance in the sub-90 nm VLSI technologies [120]. This is the particular case for leakage power, which has increased dramatically with the technology scaling and is becoming the dominant chip power dissipation [71].
Ruijing Shen, Sheldon X.-D. Tan, Hao Yu
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