Results 21 to 30 of about 4,335 (184)

Using SAT Solvers to Finding Short Cycles in Cryptographic Algorithms [PDF]

International Journal of Electronics and Telecommunications, 2020
A desirable property of iterated cryptographic algorithms, such as stream ciphers or pseudo-random generators, is the lack of short cycles. Many of the previously mentioned algorithms are based on the use of linear feedback shift registers (LFSR) and ...
Władysław Dudzic, Krzysztof Kanciak
doaj   +1 more source

SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS [PDF]

Proceedings on Engineering Sciences
The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator.
Suhas Shirol , Rajashekhar Shettar , Ramakrishna S , Vijay H M   +3 more
doaj   +1 more source

Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array

IEEE Journal of the Electron Devices Society, 2019
An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (
Xiaole Cui, Miaomiao Zhang, Qiujun Lin, Xiaoxin Cui, Anqi Pang   +4 more
doaj   +1 more source

Scrambling and De-Scrambling Implementation Using Linear Feedback Shift Register Method on FPGA

IJAIT (International Journal of Applied Information Technology), 2017
Digital broadband communications require a fast, functional and efficient system. In a digital communication system, a long sequence of bits '0' or '1' will inherits the loss of bit synchronization, and hence it can cause the false detection on the ...
Manda Lurina, Sugondo Hadiyoso, Rina Pudji Astuti   +2 more
doaj   +1 more source

A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator [PDF]

Engineering and Technology Journal, 2018
Built-in Self-test (BIST) is one of integrated circuit (IC) testing techniques that can be used as a pseudo-random generator for the Circuit Under Test (CUT). This paper introduces the design and simulation of a 4-bit test pattern generator (TPG) using a
Sahar Alawey
doaj   +1 more source

Secure Image Encryption Based on Compressed Sensing and Scrambling for Internet-of-Multimedia Things

IEEE Access, 2022
In this paper, we propose a secure image encryption system based on compressed sensing (CS) with a scrambling mechanism. For efficient encryption, we use a sparse measurement matrix, where the nonzero elements are generated by a linear feedback shift ...
Jaephil Choi, Nam Yul Yu
doaj   +1 more source

Using classifiers to predict linear feedback shift registers [PDF]

, 2001
Proceeding of: IEEE 35th International Carnahan Conference on Security Technology. October 16-19, 2001, LondonPreviously (J.C. Hernandez et al., 2000), some new ideas that justify the use of artificial intelligence techniques in cryptanalysis are ...
Hernández, Julio C., Isasi, Pedro, Mex-Perera, C., Ramos Álvarez, Benjamín, Sierra, José M.   +4 more
core   +3 more sources

Revolutionizing Underwater Sensor Performance: Tackling Rayleigh Scattering Challenges by Pseudo Random Noise. [PDF]

Adv Sci (Weinh)
This paper is an innovative combination of spread spectrum communication technology and optical fiber sensing technology. The interdisciplinary study provides a promising strategy to address the Rayleigh scattering‐induced parasitic in large‐scale fiber sensing system.
Hu Q, Shang F, Ma L, Wang W, Yu Y, Bian Y, Zhu X, Song J.   +7 more
europepmc   +2 more sources

A Novel Nonlinear Pseudorandom Sequence Generator for the Fractal Function

Fractal and Fractional, 2022
A pseudorandom sequence is a repeatable sequence with random statistical properties that is widely used in communication encryption, authentication and channel coding.
Yelai Feng, Huaixi Wang, Chao Chang, Hongyi Lu, Fang Yang, Chenyang Wang   +5 more
doaj   +1 more source

An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking [PDF]

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes, 2009
IP reuse is rapidly proliferating recent automated circuit design. It is facing serious challenges like forgery, theft and misappropriation of intellectual property (IP) of the design. Thus, protection of design IP is a matter of prime concern. In this paper, we propose a novel Internet-based scheme to tackle this problem.
Raju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen Sarma   +3 more
openaire   +1 more source