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Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”
IEEE Access, 2020 In the above article [1], R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued ...
Daniel Etiemble
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Protease circuits for processing biological information
Nature Communications, 2020 In contrast to genetic circuits, here the authors develop protein biocircuits based on proteases. They show these activity-based circuits can execute Boolean logic for programmable drug delivery and perform fuzzy logic to solve a mathematical oracle ...
Brandon Alexander Holt, Gabriel A. Kwong
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Footer Voltage Controlled Dual Keeper Domino Logic with Static Switching Approach
Advances in Electrical and Electronic Engineering, 2020 In this paper, two circuits, namely Footer Voltage Controlled Dual Keeper domino logic (FVCDK) and Footer Voltage Controlled Dual Keeper with Static Switching domino logic (FVCDK-SS) are presented, in order to achieve high speed, low power consumption ...
Chirag Parashar +3 more
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Reversible logic circuit synthesis [PDF]
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design - ICCAD '02, 2002 Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requirement in the emerging field of quantum computation. We investigate the synthesis of reversible circuits that employ a minimum number of gates and contain no redundant input ...
Shende, Vivek V. +3 more
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SensorsThis work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The
Kyung-Chan An +2 more
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LOT: Logic Optimization with Testability - new transformations for logic synthesis [PDF]
, 1998 A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability.
Chatterjee, Mitrajit +2 more
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A novel genetic algorithm for evolvable hardware [PDF]
Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system.
Kalganova, T, Lambert, C, Stomeo, E
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Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations [PDF]
, 2008 Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off.
Heath, James R. +3 more
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Pushing energy savings in adiabatic logic by carbon-nanotube field effect transistors [PDF]
Advances in Radio Science, 2011 For the first time carbon nanotube (CNT) transistor based adiabatic logic (AL) was analyzed in this work and compared to CNT based static CMOS (CCNT). Static CCNT inverters are used as a reference and compared to inverters in the AL families Efficient ...
P. Teichmann +2 more
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Generalized disjunction decomposition for the evolution of programmable logic array structures [PDF]
, 2006 Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm.
Kalganova, T, Lambert, C, Stomeo, E
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