Results 21 to 30 of about 14,420,325 (254)
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
IET Computers & Digital Techniques, 2021 This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage.
Hemanth Krishna L. +4 more
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A Monotonic Early Output Asynchronous Full Adder
Technologies, 2023 This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic.
Padmanabhan Balasubramanian +1 more
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IET Circuits, Devices and Systems, 2021 Quantum‐dot cellular automata (QCA) are prospective nanotechnology with striking performance to tackle the shortcomings of complementary metal‐oxide‐semiconductor (CMOS) transistor‐based technology such as fabrication dimensions and switching speed.
Sonia Afrooz, Nima Jafari Navimipour
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De novo design of protein logic gates
Science, 2020 Designer gates Signaling in cells can occur through protein-protein interactions. Chen et al. describe the design of logic gates that can regulate protein association.
Zibo Chen +18 more
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Design of Ternary Logic and Arithmetic Circuits Using GNRFET
IEEE Open Journal of Nanotechnology, 2020 Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits.
Zarin Tasnim Sandhie +2 more
semanticscholar +1 more source
From static ternary adders to high-performance race-free dynamic ones
The Journal of Engineering, 2015 This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic.
Shirin Rezaie +4 more
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High-Speed and Energy-Efficient Carry Look-Ahead Adder
Journal of Low Power Electronics and Applications, 2022 The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder ...
Padmanabhan Balasubramanian +1 more
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TVD‐PB logic circuit based on camouflaging circuit for IoT security
IET Circuits, Devices and Systems, 2022 Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side‐channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device.
Yuejun Zhang +5 more
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Flexible memristor-based LUC and its network integration for Boolean logic implementation
IET Nanodielectrics, 2019 Memristor is a nanoscale electronic element with variable resistance that depends on the amount and direction of the charge passing through it. As a promising candidate, this memristive element opens up a new approach for the implementation of Boolean ...
Zhekang Dong +4 more
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Challenges to adopting adiabatic circuits for systems‐on‐a‐chip
IET Circuits, Devices and Systems, 2021 Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of
Krishnan S. Rengarajan +2 more
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