Robust Wavelet-Based Information Hiding through Low-Density Parity-Check (LDPC) Codes
2004In this paper, in order to mitigate the channel conditions and improve the quality of the watermark, we proposed the application of LDPC codes on implementing a fairly robust image watermarking system. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by ...
Yu Yi +3 more
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On implementation of min-sum algorithm for decoding low-density parity-check (LDPC) codes
Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE, 2004This paper is concerned with the implementation issues of the so-called min-sum algorithm (also referred to as max-sum or max-product) for the decoding of low-density parity-check (LDPC) codes. The effects of clipping threshold and the number of quantization bits on the performance of the min-sum algorithm at short and intermediate block lengths are ...
F. Zarkeshvari, A.H. Banihashemi
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Reconfigurable Low Density Parity Check (LDPC) Code Interleaving for SIO and MIMO OFDM Systems
2006 IEEE 7th Workshop on Signal Processing Advances in Wireless Communications, 2006This contribution1 derives an algorithm for optimizing the mapping of irregular and systematic Low Density Parity Check (LDPC) code word bits onto Orthogonal Frequency Division Multiplexing (OFDM) carriers in the context of a frequency selective fading channel in both, a Single-Transmit Single-Receive (SISO channel) and Multiple-Transmit Multiple ...
Markus Muck +2 more
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Bootstrapped Low Complexity Iterative Decoding Algorithm for Low Density Parity Check (LDPC) Codes
2010RRWBF (Reliability ratio based weighted bit-flipping) algorithm is one of the best hard decision decoding algorithms in performance. Recently several modifications are done to this technique either to improve performance or to lower the complexity.
Albashir Mohamed +2 more
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Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016Spin-transfer torque random access memory (STT-RAM) has emerged as a promising nonvolatile memory technology for its fast speed, small footprint and zero standby power. However, the unique and unusual high asymmetric error rates at different memory bit operations, which are proved to be far beyond the efficiency of common error correction codes (ECCs),
Bohua Li, Yukui Pei, Wujie Wen
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Reliability-Based Hybrid ARQ (RB-HARQ) Schemes Using Low-Density Parity-Check (LDPC) Codes
IEICE Transactions on Communications, 2006The Reliability-Based Hybrid ARQ (RB-HARQ) scheme, which can be used with error correcting codes using soft-input soft-output (SISO) decoders such as convolutional codes and turbo codes has been proposed. In the RB-HARQ scheme, the error rate performance is improved by selecting the retransmission bits based on Log Likelihood Ratio (LLR) of each bit in
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Implementing High Data Rate, Low Density Parity Check (LDPC) decoders for large codes using FPGAs
2015 IEEE Aerospace Conference, 2015Low Density Parity Check (LDPC) Codes offer remarkable error correction performance and therefore increase the design space for communication systems. When implementation complexity and latency are not system limitations, LDPC codes can offer near Shannon Limit performance by using large code lengths and a high number of iterations in the decoding ...
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Throughput Improvement in Vehicular Communication by Using Low Density Parity Check (LDPC) Code
2022 IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC), 2022Utpal Kumar Dey +2 more
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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures
IEEE Communications Surveys and Tutorials, 2022Oscar Ferraz, Vitor Silva, Joao Andrade
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