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A Comparative Review of Recent Advances in Decoding Algorithms for Low-Density Parity-Check (LDPC) Codes and Their Applications

Archives of Computational Methods in Engineering, 2020
M. K. Roberts, Parthibaraj Anguraj
semanticscholar   +1 more source

Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016
Spin-transfer torque random access memory (STT-RAM) has emerged as a promising nonvolatile memory technology for its fast speed, small footprint and zero standby power. However, the unique and unusual high asymmetric error rates at different memory bit operations, which are proved to be far beyond the efficiency of common error correction codes (ECCs),
Bohua Li, Yukui Pei, Wujie Wen
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Low-Density Parity Check (LDPC) Codes

2022
Jun Xu, Jun Xu, Yifei Yuan, Meiying Huang, Liguang Li, Jin Xu   +5 more
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On implementation of min-sum algorithm and its modifications for decoding low-density Parity-check (LDPC) codes

IEEE Transactions on Communications, 2005
Jiang-Jun Zhao, F. Zarkeshvari, A. Banihashemi   +2 more
semanticscholar   +1 more source

Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

IEEE Transactions on Communications, 2006
S. Hemati, A. Banihashemi
semanticscholar   +1 more source

Reliability-Based Hybrid ARQ (RB-HARQ) Schemes Using Low-Density Parity-Check (LDPC) Codes

IEICE Transactions on Communications, 2006
The Reliability-Based Hybrid ARQ (RB-HARQ) scheme, which can be used with error correcting codes using soft-input soft-output (SISO) decoders such as convolutional codes and turbo codes has been proposed. In the RB-HARQ scheme, the error rate performance is improved by selecting the retransmission bits based on Log Likelihood Ratio (LLR) of each bit in
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Implementing High Data Rate, Low Density Parity Check (LDPC) decoders for large codes using FPGAs

2015 IEEE Aerospace Conference, 2015
Low Density Parity Check (LDPC) Codes offer remarkable error correction performance and therefore increase the design space for communication systems. When implementation complexity and latency are not system limitations, LDPC codes can offer near Shannon Limit performance by using large code lengths and a high number of iterations in the decoding ...
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The capacity of low-density parity-check codes under message-passing decoding

IEEE Transactions on Information Theory, 2001
T. Richardson, R. Urbanke
semanticscholar   +1 more source

Design of capacity-approaching irregular low-density parity-check codes

IEEE Transactions on Information Theory, 2001
T. Richardson, A. Shokrollahi, R. Urbanke   +2 more
semanticscholar   +1 more source

Throughput Improvement in Vehicular Communication by Using Low Density Parity Check (LDPC) Code

2022 IEEE 12th Annual Computing and Communication Workshop and Conference (CCWC), 2022
Utpal Kumar Dey, Robert Akl, Robin Chataut   +2 more
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