Results 161 to 170 of about 8,847,760 (170)
Some of the next articles are maybe not open access.
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS
IEEE Journal of Solid-State Circuits, 2010Hong-June Park +2 more
exaly
A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications
IEEE Transactions on Nuclear Science, 2013Edoardo Charbon, Claudio Favi
exaly
Low-Jitter All-Digital Phase-Locked Loop With Novel PFD and High Resolution TDC & DCO
2016Xin Lin, Xiaoying Deng, Mingcheng Zhu
exaly
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Dongsuk Shin +5 moreopenaire +1 more source

