Results 141 to 150 of about 8,847,760 (170)

A Phase-Walk-Based True Random Number Generator Exploiting Dual-Ring Phase Jitter Comparison

IEEE Transactions on Circuits and Systems - II - Express Briefs
A True Random Number Generator (TRNG) is a critical security component that generates unpredictable random numbers based on physical entropy sources, widely used in cryptography, secure communications, and simulation.
Liang Yao, Peiyang Kang, Jia-Hao Zhang, Yao-Hua Xu, Ying Zhang, Xiumin Xu, Hua-Guo Liang, Zheng-Feng Huang, Ying-Chun Lu   +8 more
semanticscholar   +1 more source

A 0.17–1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008
null Dongsuk Shin, null Won-Joo Yun, null Hyun-Woo Lee, null Young-Jung Choi, null Suki Kim, null Chulwoo Kim   +5 more
openaire   +1 more source

A Low-Jitter Harmonic-Free All-Digital Delay-Locked Loop for Multi-Channel Vernier TDC

Sensors, 2022
Fazhan Zhao, Mengdi Zhang
exaly  

A 61-dB SNDR 700 µm² second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops

2012 Symposium on VLSI Circuits (VLSIC), 2012
Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi   +4 more
openaire   +1 more source

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

IEEE International Solid-State Circuits Conference, 2010
W. Grollitsch, R. Nonis, N. DaDalt
semanticscholar   +1 more source

Design of low power DLL with TDC for jitter suppression

Online International Conference on Green Engineering and Technologies, 2015
S. Lakshmi, Chitra Valavan
semanticscholar   +1 more source

An 18.4 GHz Low-Jitter and Fast-Locking Fractional- N Digital PLL Using Function-Reused TDC and Path-Selection BBPDs

IEEE Transactions on Microwave Theory and Techniques
Xi Meng, Haoran Li, Peng Chen, Jun Yin, Rui P. Martins, Pui-In Mak   +5 more
openaire   +1 more source

A 0.68-to-1.44 GHz low-jitter all-digital phase-locked loop with a novel PFD and a high resolution DCO in 0.μm CMOS

International Conference on Electron Devices and Solid-State Circuits, 2016
Xiaoying Deng, Yanyan Mo, Xin Lin, Ming-Cheng Zhu   +3 more
semanticscholar   +1 more source

A Low Jitter and High-Speed Flash TDC with PVT Calibration and Its Testing Methodology

Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal   +2 more
openaire   +1 more source

A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems

Advances in Intelligent Systems and Computing, 2020
Anil Singh, Alpana Agarwal
exaly