Results 131 to 140 of about 8,847,760 (170)

A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter

Microelectronics Journal, 2020
A B S T R A C T This paper presents a low jitter multiplying delay-locked loop (MDLL) with static phase offset elimination (SPOE) applied to time-to-digital converter (TDC).
Jin Wu, Shuang Chen, Kang Hu, Li-Xia Zheng, Wei-Feng Sun   +4 more
semanticscholar   +1 more source

10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm

IEEE International Solid-State Circuits Conference
The most common approach for designing a low-jitter PLL is to use a narrow loop bandwidth (BW) to naturally suppress in-band noise, including quantization noise (Q-noise). In this method, the design of a low phase-noise (PN) LC VCO is vital since its PN,
Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi   +4 more
semanticscholar   +1 more source

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment

IEEE Journal of Solid-State Circuits
This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub- $\mu $ s locking time when synthesizing millimeter-wave (mm-wave) frequencies.
Haoran Li, Tailong Xu, Xi Meng, Jun Yin, R. Martins, Pui-In Mak   +5 more
semanticscholar   +1 more source

Prototype development of a three-stage, high-precision, low-jitter, wide-range digital delay generator fully utilizing on-chip resources.

Review of Scientific Instruments
This paper introduces the design and implementation of a prototype Digital Delay Generator (DDG) characterized by high precision, low jitter, and a wide delay range, fully realized within a Field Programmable Gate Array (FPGA).
Jin-Xin Liu, Pei-Pei Deng, Juan Liu, Ying Wang   +3 more
semanticscholar   +1 more source

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

IEEE Journal of Solid-State Circuits, 2022
This article presents an 8-bit time-domain analog-to-digital converter (ADC) achieving ten-GS/s conversion speed with only two time-interleaved (TI) channels.
Juzheng Liu, Mohsen Hassanpourghadi, M. Chen   +2 more
semanticscholar   +1 more source

A Low-Jitter mm-Wave Fractional-N Sub-Sampling PLL Using a Polarity-Reversible SSPD for DTC Range Reduction

IEEE Journal of Solid-State Circuits
This article presents a millimeter-wave (mm-Wave) band fractional-N sub-sampling PLL (SSPLL) that achieves low jitter, low spur, and fast-locking time.
Haoran Li, Jin-Ge Li, Xueying Jiang, Xi Meng, Pui-In Mak, R. P. Martins, Jun Yin   +6 more
semanticscholar   +1 more source

A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces

IEEE Custom Integrated Circuits Conference, 2023
Owing to the jitter-filtering nature, a phase-locked loop (PLL) often plays as a clock driver in memory systems, cleaning out highfrequency noise present in the overall clock distribution path.
W. Jung, Hyojun Kim, Yeonggeun Song, Kwang-Hoon Lee, D. Jeong   +4 more
semanticscholar   +1 more source

A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2019
This brief presents a cascade pseudo 3-level time-to-digital converter (TDC) based on wideband phase-locked loops (PLLs) for photon time of flight measurement.
Jin Wu, Peng-Bo Zhang, Shui-Hui Shi, Li-Xia Zheng, Wei-Feng Sun   +4 more
semanticscholar   +1 more source

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2019
In this brief, we propose a hybrid phase locked loop (PLL) which employs a coarse resolution gated ring oscillator time-to-digital converter in the digital integral (I) path and a switched RC circuit in the analog proportional (P) path, which provide ...
Dongin Kim, Seonghwan Cho
semanticscholar   +1 more source

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

International journal of circuit theory and applications, 2022
J. K. Sahani, Ashutosh Kumar Singh, A. Agarwal   +2 more
semanticscholar   +1 more source