Results 111 to 120 of about 8,847,760 (170)

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops

A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops
openaire   +1 more source

320 × 240 SPAD Direct Time-of-Flight Image Sensor and Camera Based on In-Pixel Correlation and Switched-Capacitor Averaging. [PDF]

Sensors (Basel)
Kuijk M, Morsy A, Lapauw T, Van den Dries T, Nevens W, Bounouar MA, Ingelberts H, Van Nieuwenhove D.   +7 more
europepmc   +1 more source

Radiation Hardened LIDAR Sensor: Conceptual Design, Testing, and Performance Evaluation. [PDF]

Sensors (Basel)
Jonasson ET, Kuhlmann C, Wood C, Skilton R.   +3 more
europepmc   +1 more source

High Spatial Resolution Detector System Based on Reconfigurable Dual-FPGA Approach for Coincidence Measurements. [PDF]

Sensors (Basel)
Cautero M, Garzetti F, Lusardi N, Sergo R, Stebel L, Costa A, Bonanno G, Ronconi E, Geraci A, Píš I, Magnano E, Pedio M, Cautero G.   +12 more
europepmc   +1 more source

Design of a Mobile and Electromagnetic Emissions-Compliant Brain Positron Emission Tomography (PET) Scanner. [PDF]

Sensors (Basel)
Fuentes C, Béguin M, Commichau V, Flock J, Lomax AJ, Makkar S, McNamara K, Prior JO, Ritzer C, Winterhalter C, Dissertori G.   +10 more
europepmc   +1 more source

An ADPLL-Based GFSK Modulator with Two-Point Modulation for IoT Applications. [PDF]

Sensors (Basel)
Kim NS.
europepmc   +1 more source

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A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC

2023 IEEE 15th International Conference on ASIC (ASICON), 2023
This paper presents a low jitter multiplying delay-locked loop (MDLL) with a current-controlled delay line (DL) for high-precision time-to-digital converter (TDC).
Hujun Jia
exaly   +3 more sources

A 320-Fs RMS Jitter And – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

IEEE Journal of Solid-State Circuits, 2019
This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer- ${N}$ digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently.
Jaehyouk Choi, Taeho Seong, Yongsun Lee
exaly   +3 more sources

A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC

AEU - International Journal of Electronics and Communications, 2020
Abstract In the present work, an all digital phase locked loop architecture (ADPLL) employing a bang-bang phase frequency detector (BB-PFD) and the 3-bit flash based time to digital converter (TDC) is designed to enhance the jitter and locking time performance.
Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal   +2 more
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Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO

2016 29th IEEE International System-on-Chip Conference (SOCC), 2016
A low-jitter and wide output frequency range ADPLL was proposed in this paper. The adopted PFD based on sense-amplifier flip-flop (SAFF) can effectively improve the jitter performance. The novel DCO with cascading structure consists of a coarse-tuning delay chain and a fine-tuning interpolator, obtaining both wide frequency tuning range and high ...
Xiaoying Deng, Yanyan Mo, Xin Lin, Mingcheng Zhu 0002   +3 more
openaire   +2 more sources