Results 121 to 130 of about 8,847,760 (170)
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A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems
Intelligent Systems with Applications, 2019This work represents a high resolution and low jitter 5-bit Flash Time to Digital converter (TDC) which concurrently achieves low power and improved periodic jitter. To minimize quantization error τQ and attain high resolution, equally spaced flash TDC is calibrated with least mean square algorithm (LMS).
Jagdeep Kaur Sahani +2 more
openaire +2 more sources
IEEE Transactions on Microwave Theory and Techniques
This work presents an 18.4 GHz fractional-N digital phase-locked loop (DPLL) featuring a novel digital phase and frequency detector (PFD), which combines the functions of the time-to-digital converter (TDC) and the path-selection bang-bang phase ...
Peng Chen, Pui-In Mak, Jun Yin
exaly +2 more sources
This work presents an 18.4 GHz fractional-N digital phase-locked loop (DPLL) featuring a novel digital phase and frequency detector (PFD), which combines the functions of the time-to-digital converter (TDC) and the path-selection bang-bang phase ...
Peng Chen, Pui-In Mak, Jun Yin
exaly +2 more sources
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
IEEE Journal of Solid-State Circuits, 2015 A digital fractional-N PLL that employs a high resolution TDC and a truly Delta Sigma fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out Delta
A. Elkholy +4 more
semanticscholar +2 more sources
A Multiplying Delay-Locked Loop design with low jitter and high linearity
Information and Communication Technologies and Accessibility, 2022In this paper, a Multiplying Delay-Locked Loop (MDLL) for high-precision Time to Digital Converter(TDC) is proposed, which has low jitter and high delay linearity.
Jiahao Hu +5 more
semanticscholar +1 more source
A 4-GHz Low-Power TDC-Based All Digital PLL Having 9.6mW and 1.2ps Rms Jitter
2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals, 2011Jayol Lee
exaly +2 more sources
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL
International SoC Design Conference, 2021A 7.68 GHz fast-lock digital multiplying delay-locked loop (MDLL) is presented. Implemented in a 40-nm 1.2-V CMOS process, the proposed MDLL achieves an output frequency of 7.68 GH with a high frequency multiplication factor N = 64.
Junghoon Jin +6 more
semanticscholar +1 more source
A 0.17–1.4GHz Low-Jitter All Digital DLL With TDC-Based DCC Using Pulse Width Detection Scheme
European Solid-State Circuits Conference, 2008Chulwoo Kim +2 more
exaly +2 more sources
IEEE International Solid-State Circuits Conference, 2018 To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture.
Taeho Seong +3 more
semanticscholar +2 more sources
European Solid-State Circuits Conference, 2016 We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator ...
Ying Wu +4 more
semanticscholar +2 more sources