Results 201 to 210 of about 2,025,203 (269)
A Low-Noise, Low-Power, and Wide-Bandwidth Regulated Cascode Transimpedance Amplifier with Cascode-Feedback in 40 nm CMOS. [PDF]
Sensors (Basel)Zhang X, Zhao Y, Yu G, Lu Z, Wang C.
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Low-Power Flexible Classifier Chip for Atrial Fibrillation Detection. [PDF]
IEEE Trans Circuits Syst Artif IntellSanchez J +4 more
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Real-Time Parking Space Management System Based on a Low-Power Embedded Platform. [PDF]
Sensors (Basel)Kim K, Lee J, Jeong I, Jung J, Cho J.
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The impact of EEG preprocessing parameters on ultra-low-power seizure detection. [PDF]
EpilepsiaReisinger P +8 more
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Low-Power Short-Pulse-Width Fractional Microneedle Radiofrequency Relieves LL37-Induced Rosacea-Like Skin Inflammation. [PDF]
J Cosmet DermatolXu Z +11 more
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IEEE Transactions on Computers, 1999
The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology.
Alberto Nannarelli, Tomás Lang
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The general objective of our work is to develop methods to reduce the energy consumption of arithmetic modules while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here, we illustrate some techniques for dividers realized in CMOS technology.
Alberto Nannarelli, Tomás Lang
openaire +1 more source
Proceedings of the 10th Great Lakes symposium on VLSI, 2000
The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer.
Bibhudatta Sahoo 0002 +2 more
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The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer.
Bibhudatta Sahoo 0002 +2 more
openaire +1 more source
2008 IEEE International Test Conference, 2008
The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and ...
Swapnil Bahl +2 more
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The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and ...
Swapnil Bahl +2 more
openaire +1 more source
Low-power software for low-power people
Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2002We have been working towards portable terminals that interact with the user via speech synthesis, automatic speech recognition, and handwriting recognition. Our work includes the development of hardware platforms, operating system (OS) and application software; and the adaptation of signal processing algorithms to these systems.
J.H. Snyder, J.B. McKie, B.N. Locanthi
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