Results 151 to 160 of about 14,704,035 (301)
Integration of Reconfigurable p‐Bit and 1R Crossbar Array for Memristive Probabilistic Computing
Advanced Science, EarlyView.A memristive probabilistic computing system is demonstrated by integrating stochastic p‐bits based on volatile memristors with a 1R crossbar array encoding interaction weights. The system performs weighted‐sum operations across the array and updates p‐bits iteratively.
Keunho Soh +7 more
wiley +1 more source
High-Speed Low Power Design in CMOS
, 2004 Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption.
Usmani, S. H. +2 more
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Scalable MoS2/Si Photodiode Arrays From Roll‐to‐Roll Mechanical Exfoliation
Advanced Science, EarlyView.A dry roll‐to‐roll route transforms mechanically exfoliated MoS2 flake networks into silicon‐integrated photodiode arrays. The MoS2/Si junctions generate photovoltaic output without applied bias, allowing illuminated pixels to locate light spots and reconstruct simple images.
Yigit Sozen +2 more
wiley +1 more source
An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags
, 2009 An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range.
Feng P (Feng Peng) +3 more
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Ultra-Low Power CMOS Logic and Photodetection in WSe<sub>2</sub> Semiconductors by Selective Area Plasma Doping. [PDF]
ACS Appl Mater InterfacesLin JJ +15 more
europepmc +1 more source
Neuromorphic Devices and Computing for Sensing, Memory, and Control
Advanced Science, EarlyView.This review introduces neuromorphic devices made from diverse materials. These devices mimic neuronal functions and architectures and, when integrated with artificial or biological computing, can form closed loops with neurons for pressure, optical, acoustic, and biochemical sensing and modulation.
Zhengguang Zhu +2 more
wiley +1 more source
Low-Power Logic Styles: CMOS vs CPL
, 1996 Recently reported logic style comparisons based on full-adder circuits showed complementary pass-transistor logic (CPL) to be much more power efficient than conventional CMOS. New comparisons performed on more efficient CMOS circuit implementations and a
Reto Zimmermann, Rajiv Gupta
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Highly Miniaturized, Low-Power CMOS ASIC Chip for Long-Term Continuous Glucose Monitoring. [PDF]
J Diabetes Sci TechnolGudlavalleti RH +8 more
europepmc +1 more source
Advanced Science, EarlyView.As CMOS technology approaches fundamental energy limits, new paradigms for low‐power information processing are required. Magnetic systems are attractive for their spin transport, yet current‐induced magnetization control is energy inefficient. Multiferroic heterostructures enable energy‐efficient electric field manipulation of magnetism.
Donghyeon Lee +3 more
wiley +1 more source
Low-power techniques for CMOS SRAM design
, 1997 This project attempts on exploring some low-power circuit techniques for CMOS SRAM design. The interests of this work are focused on the power reduction of the memory cell array, current-mode sensing circuit and FIFO memory.Master of ...
Wang, Hai Bo
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