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1998
From the Publisher: This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.
Anantha Chandrakasan +1 more
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From the Publisher: This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.
Anantha Chandrakasan +1 more
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Wire Topology Optimization for Low Power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits.
Paul Zuber +4 more
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International Journal of High Speed Electronics and Systems, 1994
A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS.
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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS.
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A Low-Power Wideband CMOS LNA for WiMAX
IEEE Transactions on Circuits and Systems II: Express Briefs, 2007In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply.
Ahmed Amer +2 more
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Low-power design of combinational CMOS networks
East-West Design & Test Symposium (EWDTS 2013), 2013An approach to logic synthesis using CMOC element library is suggested, which allows to minimize the area and the average value of the dissipated power of microcircuit implemented on CMOC VLSI chip. The case of synthesis of combinational CMOC networks is considered when key schematic solutions, such as clock frequency and supply voltage, are assigned ...
Dmitry I. Cheremisinov +1 more
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Low-power CMOS PLL for clock generator
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003This paper presents a design of phase-locked loop suitable for the clock generation of DSP applications. The challenge of a low-jitter PLL is observed in the design tradeoff between noise contributions and bandwidth choice. An extra logic scheme with a PFD (phase/frequency detector) is applied in the lock detection.
Wen-Chi Wu +3 more
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CMOS RF design-the low power dimension
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 2002In many wireless applications power consumption of an RF-IC is more important than integration level due to battery life time considerations. This has been a weak point for CMOS, which has prevented its general acceptance for demanding applications such as cellular and paging. Growing attention is now being paid to low power design of CMOS RF ICs. This
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Transistor sizing for low power CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996A direct approach to transistor sizing for minimizing the power consumption of a CMOS circuit under a delay constraint is presented. In contrast to the existing assumption that the power consumption of a static CMOS circuit is proportional to the active area of the circuit, it is shown that the power consumption is a convex function of the active area.
Manjit Borah +2 more
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An ultra low power 2.4GHz CMOS VCO
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2004A low power voltage-controlled oscillator (VCO) for IEEE 802.11b direct conversion receiver is demonstrated. The VCO is fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is -73.62dBc/Hz@600 kHz offset and -82.44dBc/Hz@1MHz offset at 2.4GHz.
Christina F. Jou +2 more
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A 24GHz low-power CMOS receiver design
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008A 24 GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator ...
Chen-Yuan Chu +4 more
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