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Low-Power CMOS Digital Design [PDF]
IEEE Journal of Solid-State Circuits, 1992 Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with ...
R W Brodersen, A P Chandrakasan, S Sheng
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Low-power MEMS-based CMOS Transceivers
2023 International Conference on IC Design and Technology (ICICDT), 2023An ISM 915-MHz FSK transceiver for low power internet-of-things (IoT) applications is presented in this paper. The system supports a shared antenna interface of FSK-matched filter for TRX and a matching network for the FSK RX. To consume less power, the transmitter employs an adaptive fast switching technique for FSK modulator, and uses a high-Q MEMS ...
Tang, Kai +5 more
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[1991] Proceedings. First Great Lakes Symposium on VLSI, 2002
A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable.
John A. Canaris, Sterling R. Whitaker
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A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable.
John A. Canaris, Sterling R. Whitaker
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Energy recovery for low-power CMOS
Proceedings Sixteenth Conference on Advanced Research in VLSI, 2002Energy recovery, as a means to trade off power dissipation for performance in CMOS logic circuits, is analyzed and investigated. A mathematical model is presented to estimate the efficiency for two energy-recovery approaches under varying conditions of voltage swing, transition time, and MOS device parameters. This model can be directly compared to the
William C. Athas, Nestoras Tzartzanis
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Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 2002
Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its ...
Kei-Yong Khoo, Alan N. Willson Jr.
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Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its ...
Kei-Yong Khoo, Alan N. Willson Jr.
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A low-power CMOS analog multiplier
IEEE Transactions on Circuits and Systems II: Express Briefs, 2006A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance,
Chunhong Chen, Zheng Li
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Proceedings of the 39th conference on Design automation - DAC '02, 2002
An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low ...
Michiel Steyaert, Peter J. Vancorenland
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An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low ...
Michiel Steyaert, Peter J. Vancorenland
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An ultra low power CMOS motion detector
IEEE Transactions on Consumer Electronics, 2009This paper proposes a CMOS motion detector which consumes extremely low power. CMOS image sensor pixels in this motion detector senses image and image data are converted into just one-bit by using clocked comparators. Because using one-bit data makes additional processing units simple, total power consumption of this CMOS motion detector can be reduced.
Sang-hyeok Yang +4 more
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A low-power CMOS RF power detector
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012This paper describes the design and implementation of a low-power wide dynamic range radio-frequency (RF) power detector in a standard 0.18-μm CMOS process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier.
Siraporn Sakphrom +1 more
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Low-power CMOS continuous-time filters
IEEE Journal of Solid-State Circuits, 1996A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance.
Rajesh H. Zele, David J. Allstot
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