Results 61 to 70 of about 14,986,572 (302)
Run-time power and performance scaling in 28 nm FPGAs [PDF]
, 2014 The ability of scaling power and performance at run-time enables the creation of computing systems in which energy is consumed in proportion of the work to be done and the time available to do it.
Nunez-Yanez, Jose L +1 more
core +1 more source
FEBS Letters, EarlyView.We present robust protocols for the preparation of supported lipid bilayers (SLBs) incorporating either Salmonella smooth LPS or outer membrane vesicles (OMVs). We use a combination of quartz crystal microbalance with dissipation (QCM‐D) and fluorescence microscopy to both characterize the SLBs of various compositions and to probe their interactions ...
Hudson P. Pace +6 more
wiley +1 more source
Design and analysis strategies for robust microbiome ageing research
FEBS Letters, EarlyView.The gut microbiome changes with age and associates with age‐related morbidity and mortality, establishing it as a potential biomarker and intervention target for ageing. Realising this potential requires methodological rigour, yet distinguishing biological signals from methodological artefacts remains challenging across cohorts. This review provides an
Mark Olenik +5 more
wiley +1 more source
IEEE Access, 2020 In this paper, a minimum-phase response fourth-order boost dc-dc converter (FBDC) exhibiting continuous input and output current is proposed. A voltage-mode controller is adopted to this converter to perform bus voltage regulation in a low voltage low ...
Ashima Kulshreshtha +2 more
doaj +1 more source
Low-power and low-voltage D-latch
Electronics Letters, 1998 A novel low-power and low-voltage static D-latch is presented using weak transistors where the driving capability is not crucial. Based on the HSPICE simulation with 0.8 /spl mu/m technology file from IME, power consumption has been reduced by 11% to 34%. The lowest operating voltage is 1.6 V.
null Liu Po Ching, null Ong Geok Ling
openaire +1 more source
Proposal for a Ultra Low Voltage NAND gate to withstand Power Analysis Attacks
, 2008 —In this paper we promote the Ultra Low Voltage (ULV) NAND gate to replace either partly or entirely the encryption block of a design to withstand power analysis ...
Keywords—differential Power Analysis (dpa +1 more
core
A power sharing series power BJT array with isolated low voltage control for AC power control applications [PDF]
, 2006 A technique for a continuously variable AC resistance using a series BJT array is presented. This array provides high power dissipation capability and uniform voltage and power distribution across the individual transistors. The array, controlled using a
Paul Cho +3 more
core +1 more source
Reconstructing enzyme evolution by protein engineering
FEBS Letters, EarlyView.Natural enzyme evolution can be retraced by protein engineering methods such as directed evolution, rational design, and ancestral sequence reconstruction. These approaches reveal how enzymes emerged from ligand‐binding scaffolds, developed varying substrate preferences, formed oligomeric complexes, adapted to environmental changes, and evolved novel ...
Lukas Drexler +2 more
wiley +1 more source
Investigating transcription factor dynamics in health and disease using FRAP
FEBS Letters, EarlyView.FRAP analysis of GFP‐tagged transcription factors reveals how molecular mobility and target engagement change in response to drug treatment. By combining live‐cell imaging, quantitative model fitting, and statistical analysis, this approach uncovers transcription factor dynamics linked to disease mechanisms, providing a powerful framework for ...
Kannan Govindaraj +3 more
wiley +1 more source
A Sub-1-V Nanopower MOS-Only Voltage Reference
Journal of Low Power Electronics and ApplicationsA novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle.
Siqi Wang +5 more
doaj +1 more source