Results 231 to 240 of about 2,012,876 (269)

Low-power multimedia RISC

IEEE Micro, 1995
Battery-powered multimedia systems challenge designers to pack enormous signal-processing power into a low-power chip. The V830 chip achieves this by combining a special instruction set and fast, 32-bit parallel multiply-adder with internal RAM for quicker memory accesses. This gives the newest entry in the V800 series signal-processing capabilities as
Kouhei Nadehara, Ichiro Kuroda, Masayuki Daito, Takashi Nakayama   +3 more
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Low-power chips for high-powered handhelds

Computer, 2003
Handheld devices have added more and more functionality over the past couple of years. Advances in wireless networks have contributed to this trend. However, the major factor has been the development of more powerful mobile processors. New mobile chips have given smart cellular phones, PDAs, and intelligent pagers the capability to run faster, access ...
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Low Jitter and Low Power PLL：Towards The Utopia

2019 International SoC Design Conference (ISOCC), 2019
A PLL usually consists of a voltage controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a frequency divider with ratio N (÷N). Every component will add noise and power to the PLL.
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Technology mapping for low power

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999
Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several research attentions. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch.
Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang   +2 more
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Low-voltage Low-power Amplifiers

1993 IEEE International Symposium on Circuits and Systems, 2002
Johan H. Huijsing, Ron Hogervorst, Klaas-Jan de Langen   +2 more
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Low power memory design

Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors, 2003
In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of storage bandwidth optimization (SBO) techniques to simplify the conflict graph and (ii) use of memory exploration techniques to determine the best memory configuration ...
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Design of low-power libraries

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), 2002
The design of a low-power standard cell library has to satisfy several requirements, such as low activity of the internal nodes, reduced parasitic capacitances and the ability to work at very low Vdd. This paper presents some of these aspects with design examples of basic cells of a low-power library.
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A decade of low-power wireless

2013 IEEE International Conference on Pervasive Computing and Communications Workshops (PERCOM Workshops), 2013
Energy has always been the number one issue in wireless sensor networks, both because of the resource constraints of sensor nodes and because of the need for untethered operation. In particular, the energy footprint of wireless communication has been the object of a great deal of interest over the past decade.
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Wireless power transfer based on novel physical concepts

Nature Electronics, 2021
Mingzhao Song, Prasad Jayathurathnage, Esmaeel Zanganeh   +2 more
exaly  

Increase in frequency of nuclear power outages due to changing climate

Nature Energy, 2021
Ali Ahmad
exaly