Results 221 to 230 of about 2,012,876 (269)

A low-power CMOS RF power detector

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012
This paper describes the design and implementation of a low-power wide dynamic range radio-frequency (RF) power detector in a standard 0.18-μm CMOS process. The proposed circuit includes a root-mean-square (RMS) power detector and a logarithmic amplifier.
Siraporn Sakphrom, Apinunt Thanachayanont   +1 more
openaire   +1 more source

Peak power reduction in low power BIST

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), 2002
In order to meet the power and reliability constraints, it is important to reduce both average and peak power during BIST operations. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG) with peak power. reduction. The technique can be used during on-line testing of large circuits requiring low power consumption.
Xiaodong Zhang 0010, Kaushik Roy 0001
openaire   +1 more source

Low-power mechanism with power block management

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006
In this paper, a low power mechanism with power block management is proposed to reduce the power consumption in DSP chips. Because the digital signal processing (DSP) chips use many functional units in the data-path to achieve parallel processing, the unnecessary functional units are also executed simultaneously, and they dissipate the power.
Kuo-Chuan Chao, Kuan-Hung Chen, Yuan-Sun Chu, Jiun-In Guo   +3 more
openaire   +1 more source

Embedded power supply for low-power DSP

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
The use of dynamically adjustable power supplies as a method to lower power dissipation in DSP is analyzed. Power can be reduced substantially without sacrificing performance in fixed-throughput applications by slowing the clock and lowering supply voltage instead of idling when computational workload varies.
Vadim Gutnik, Anantha P. Chandrakasan
openaire   +1 more source

On low power test and low power compression techniques

2018
<p>With the ever increasing integration capability of semiconductor technology, today's large integrated circuits require an increasing amount of data to test them which increases test time and elevated requirements of tester memory.</p> <p>At the same time, as VLSI design sizes and their operating frequencies continue
Elham Khayat Moghaddam, David R. Andersen, Xiaodong Wu, Hantao Zhang, Jon G. Kuhl, Janusz Rajski, Sudhakar M. Reddy   +6 more
openaire   +1 more source

Low-swing/low power driver architecture

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 2003
A new low-swing/low-power CMOS driver architecture for VLSI applications is proposed. The architecture based on low swing technique using the conventional CMOS static logic. Simulation results based on the proposed design show significant improvements in both power dissipation and power-delay product compared to other low swing techniques driver ...
Abdoul Rjoub, Odysseas G. Koufopavlou
openaire   +1 more source

Low-voltage low-power LVDS drivers

IEEE Journal of Solid-State Circuits, 2005
Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications.
Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson   +3 more
openaire   +1 more source

Low voltage, low power operational amplifier

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2004
A 0.8 V folded cascode operational amplifier was designed in 0.18-/spl mu/m standard CMOS technology. Emphasis was placed on observing the low voltage design and using current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing threshold voltage.
Shahab Ardalan, Kaamran Raahemifar, Fei Yuan 0005   +2 more
openaire   +1 more source

Audio at low and high power

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008
An overview is presented of recent developments in the analog boundaries of the audio chain. The main focus is on class-D amplifiers that are by now almost standard in consumer applications and emerging in automotive and mobile applications as well. Further, an overview of the state-of-the-art in A/D and D/A conversion is given.
Marco Berkhout, Lucien J. Breems, Ed van Tuijl   +2 more
openaire   +1 more source

A low power asynchronous DES

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002
Nowadays, there are many Cryptographic Applications that demand both high speed and low power. In order to meet this requirement, we have designed a new asynchronous Data Encryption Standard (DES) data encryption chip and decided that can be used in contactless smart cards.
Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan   +3 more
openaire   +1 more source