Results 251 to 260 of about 17,876,451 (313)
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2013
This chapter presents architectural considerations for the proposed transceiver. Four main aspects are identified as essential for ultra-low power consumption. First, the definition of the receiver architecture is a fundamental issue as it affects the structure and design requirements of individual blocks.
Jens Masuch, Manuel Delgado-Restituto
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This chapter presents architectural considerations for the proposed transceiver. Four main aspects are identified as essential for ultra-low power consumption. First, the definition of the receiver architecture is a fundamental issue as it affects the structure and design requirements of individual blocks.
Jens Masuch, Manuel Delgado-Restituto
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Low Power/Low Noise Electronics
2001Abstract : Army communication systems have several major limitations, including limited bandwidth, low throughput, dependence upon terrestrial line-of-sight, lack of full mobility and limited support for intelligence and imagery requirements. Additional requirements include low probability of intercept, jam resistant, multi-frequency systems and low ...
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Versatile low power media access for wireless sensor networks
ACM International Conference on Embedded Networked Sensor Systems, 2004J. Polastre, Jason L. Hill, D. Culler
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Low-voltage Low-power Amplifiers
1993 IEEE International Symposium on Circuits and Systems, 2002J.H. Huijsing +2 more
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On low power test and low power compression techniques
2018With the ever increasing integration capability of semiconductor technology, today’s large integrated circuits require an increasing amount of data to test them which increases test time and elevated requirements of tester memory. At the same time, as VLSI design sizes and their operating frequencies continue to increase, timing-related defects are ...
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A Low Power, Fully Event-Based Gesture Recognition System
Computer Vision and Pattern Recognition, 2017A. Amir +15 more
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Two-dimensional spintronics for low-power electronics
Nature Electronics, 2019Xiaoyang Lin +3 more
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2012
Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores ...
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Dynamic random access memory (DRAM) is a volatile random access memory and the memory cell consists of a cell transistor and a capacitor [1–3], as shown in Fig. 5.1. The cell transistor is used to connect a storage node (N) and a data-line (DL) by activating a word-line (WL), while the capacitor, connected between N and the plate (PL), stores ...
openaire +1 more source