Results 261 to 270 of about 23,384 (296)

An Memory polynomial model for power amplifiers

2008 International Conference on Communications, Circuits and Systems, 2008
In this paper, an envelope Memory polynomial (MP) model is introduced to describe dynamic input -output characteristics of RF power amplifiers. In the modeling approach, we use a new truncation method and an established nonlinear time series method to determine model structure.
null Wang Huadong, null Bao Jingfu, null Wu Zhengde, null Huang Jingfu   +3 more
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Certification of Safe Polynomial Memory Bounds

2011
In previous works, we have developed several algorithms for inferring upper bounds to heap and stack consumption for a simple functional language called Safe. The bounds inferred for a particular recursive function with n arguments takes the form of symbolic n-ary functions from (R+)n to R+ relating the input argument sizes to the number of cells or ...
Javier de Dios, Ricardo Peña
openaire   +1 more source

Memory polynomial predistorter based on the indirect learning architecture

Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE, 2003
Power amplifiers (PAs) are inherently nonlinear devices and are used in virtually all communications systems. Digital baseband predistortion is a highly cost effective way to linearize PAs, but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as WCDMA, PA memory effects can no longer be
Lei Ding 0001, Guo Tong Zhou, Dennis R. Morgan, Zhengxiang Ma, J. Stevenson Kenney, Jaehyeong Kim, Charles R. Giardina   +6 more
openaire   +1 more source

Polynomial-time algorithm for on-chip scratchpad memory partitioning

Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03, 2003
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main challenge in SPM design is mapping memory locations to scratchpad locations.
Federico Angiolini, Luca Benini, Alberto Caprara   +2 more
openaire   +1 more source

Three-Layered Biased Memory Polynomial for Dynamic Modeling and Predistortion of Transmitters With Memory

IEEE Transactions on Circuits and Systems I: Regular Papers, 2013
This paper proposes a new three-layered biased memory polynomial for behavioral modeling and digital predistortion of highly nonlinear transmitters/power amplifiers (PAs) for 3G wireless applications. The proposed model considers the possibility that the nonlinearity order of the dynamic part of the PA characteristics is different from the nonlinearity
Meenakshi Rawat, Fadhel M. Ghannouchi, Karun Rawat   +2 more
openaire   +1 more source

A memory polynomial predistorter for compensation of nonlinearity with memory effects in WCDMA transmitters

2009 International Conference on Communications, Circuits and Systems, 2009
Power amplifiers (PAs) are inherently nonlinear devices and are used in all transmitters of a communications equipment. To improve the performance of telecommunication channels, digital baseband predistortion is employed to compensate for PA nonlinearities. But most existing architectures base on the memoryless PA model.
null Jing Zhang, null Songbai He, null Shirong Yin   +2 more
openaire   +1 more source

Combined memory polynomial model for Doherty power amplifiers with memory effects

2012 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 2012
This paper presents a combined memory polynomial model for Doherty power amplifiers with memory effects. The model combines the memory polynomial model with an envelope memory term. Levenberg-Marquardt Method is applied to estimate the model parameters.
Jianfeng Zhai, Lei Zhang, Jing Xia, Jianyi Zhou, Xiaowei Zhu, Wei Hong   +5 more
openaire   +1 more source

Parallel univariate polynomial factorization on shared-memory multiprocessors

Proceedings of the international symposium on Symbolic and algebraic computation, 1990
Using parallelism afforded by shared-memory multiprocessors to speed up systems for polynomial factorization is discussed. The approach is to take the fastest known factoring algorithm for practical purposes and parallelize key parts of it. The univariate factoring algorithm consists of two major tasks (a) factoring modulo small integer primes and (b ...
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Memory polynomial digital predistortion for power amplifiers

2007 International Symposium on Communications and Information Technologies, 2007
Due to the development of wireless communication systems, the linearity requirement of power amplifiers (PAs) is very stringent. A new concept was proposed to model a predistorter directly without modeling a PA firstly. The algorithm can not only improve the linearity of amplifier, but also adjust the gain of PAs dependently.
null Cuiping Yu, null Yongsheng Feng, null Yuanan Liu, null Gang Xie   +3 more
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A Stable Recursive Algorithm for Memory Polynomial Predistorter

MILCOM 2007 - IEEE Military Communications Conference, 2007
The memory polynomial model has been used for predistorter design, which will result in numerical instabilities when higher order terms are included. In this paper, basing on least square estimation, a recursive algorithm for indirect learning structure predistorter is introduced. Simulation results show that higher order (higher than 7th-order) memory
Xu Lingjun, Wu Xiaoguang, Zhang Min, Kang Guixia, Zhang Ping   +4 more
openaire   +1 more source