MESI protocol for multicore processors based on FPGA
Periodicals of Engineering and Natural Sciences (PEN), 2021 In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task ...
Ibrahim A. Amory +2 more
+8 more sources
Are portable ankle brachial pressure index measurement devices suitable for hypertension screening? [PDF]
PLoS ONE, 2023 ObjectiveIn a large-scale population cardiovascular screening programme, peripheral artery disease (PAD) and hypertension would ideally be rapidly assessed using a single device.
Justyna Janus +4 more
doaj +2 more sources
Cache coherency controller for MESI protocol based on FPGA
International Journal of Electrical and Computer Engineering (IJECE), 2021 In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job.
Mays K. Faeq, Safaa S. Omran
openaire +3 more sources
Ultra-Low-Dose versus Normal-Dose Scan Protocol of Planmeca ProMax 3 D Mid CBCT machine in Detection of Second Mesi buccal Root Canal in Maxillary Molars: An ex vivo study [PDF]
Egyptian Dental Journal, 2019 Objective: The aim of this study was to compare the ability of Normal and Ultra-Low-Dose protocols of Planmeca Promax 3 D Mid CBCT unit with different voxel sizes in detection of MB2 canal.Materials and Methods: This study was conducted on 36 extracted human maxillary first and second molars.
Dina Ahmed
openaire +2 more sources
International Journal of Computer Applications, 2014 ABSTRACT To improve the efficiency of a processor to work with data, cache memories are used to compensate the latency delay to access data from the main memory. But because of the installation of different caches in different processors in a shared memory architecture, makes it very difficult to maintain consistency between the cache memories of ...
Mamatha S. Nair, Somdip Dey
openaire +2 more sources
A cross-sectional study in type 2 diabetes patients reveals that elevated pulse wave velocity predicts asymptomatic peripheral arterial disease associated with age and diabetes duration [PDF]
International Journal of Cardiology: Heart & Vasculature, 2023 Background: Peripheral arterial disease (PAD) reduces functional capacity and raises cardiovascular risks, but underdiagnosis is common, resulting in less comprehensive care than other cardiovascular conditions.
Dora Gašparini +3 more
doaj +2 more sources
Proposal New Cache Coherence Protocol to Optimize CPU Time through Simulation Caches [PDF]
Engineering and Technology Journal, 2016 The cache coherence is the most important issue that rapidly affected the performance of a multicore processor as a result of increasing the number of cores on chip multiprocessors and the shared memory program that will be run on these processors ...
Luma Fayeq Jalil +2 more
doaj +1 more source
MESI Cache Coherence Simulator for Teaching Purposes
CLEI Electronic Journal, 2009 Nowadays, the computational systems (multi and uniprocessors) need to avoid the cache coherence problem. There are some techniques to solve this problem. The MESI cache coherence protocol is one of them.
Juan Gómez-Luna +2 more
doaj +1 more source
Locality-Adaptive Parallel Hash Joins Using Hardware Transactional Memory [PDF]
, 2016 Previous work [1] has claimed that the best performing implementation of in-memory hash joins is based on (radix-)partitioning of the build-side input.
Madden, S, Pirk, H, Shanbhag, A
core +1 more source
Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis
IEEE Access, 2017 In previous work, a new network switch architecture, hybrid circuit-switched (HCS) network, has been proposed and evaluated. In doing so, it has been studied for use in a multi-processor system, with a focus on power and throughput.
Sizhao Li, Donghui Guo
doaj +1 more source