Results 11 to 20 of about 28,883 (254)

Miller effect suppression of tunnel field‐effect transistors (TFETs) using capacitor neutralisation

open access: closedElectronics Letters, 2016
A novel method of suppressing the Miller effects of tunnel field‐effect transistors (TFETs) is proposed by using capacitor neutralisation. Since TFETs suffer from more severe Miller effects than metal‐oxide‐semiconductor FETs, conventional ways such as short‐gate structures are not sufficient to fully suppress the Miller effects of TFETs.
Woo Young Choi
exaly   +4 more sources

Single Miller frequency compensation: Three stage CMOS

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
A simple and efficient frequency compensation network is exploited for a three-stage amplifier. Single Miller capacitor at the output of a differential stage forms compensation network.
Ilghar Rezaei   +3 more
doaj   +3 more sources

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits [PDF]

open access: yesIEEE Transactions on Circuits and Systems I: Regular Papers, 2009
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs).
Delgado Restituto, Manuel   +2 more
core   +3 more sources

Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained.
Ilghar Rezaei   +3 more
doaj   +1 more source

Improved Frequency Compensation Technique for Three-Stage Amplifiers

open access: yesJournal of Low Power Electronics and Applications, 2021
Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time.
Alejandro Roman Loera   +4 more
doaj   +1 more source

A fast transient response on-chip low-dropout regulator

open access: yesDianzi Jishu Yingyong, 2023
: Based on dual active feedback with miller capacitor compensation (DAFMCC), a novel single pole system of capacitor-less on-chip low-dropout (LDO) voltage regulator circuit is presented.
Xu Qinghao
doaj   +1 more source

CMOS low dropout linear regulator with single Miller capacitor [PDF]

open access: yesElectronics Letters, 2006
A 2–5V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 µm CMOS process and the active chip area is 485×586 µm. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.
Huang, W.J., Lu, S.H., Liu, S.I.
openaire   +2 more sources

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

open access: yesIEEE Access, 2022
This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution ...
Hamed Aminzadeh   +2 more
doaj   +1 more source

Design of a high stability LDO without off-chip capacitor

open access: yesDianzi Jishu Yingyong, 2020
This paper is aimed at researching and designing LDOs without off-chip capacitors. Whether the LDO can stabilize the output voltage when there is no external capacitor is studied. Based on this, a new type of high-stability LDO structure with no off-chip
Huo Dexuan, Zhang Guojun
doaj   +1 more source

Recycling folded cascode two-stage CMOS amplifier

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V.
Ilghar Rezaei   +3 more
doaj   +1 more source

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