Results 11 to 20 of about 1,040 (218)
Recycling folded cascode two-stage CMOS amplifier
Memories - Materials, Devices, Circuits and Systems, 2023 In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V.
Ilghar Rezaei +3 more
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Extraction of circuit parameters using multi-objective genetic algorithm for design of non-linearly compensated operational amplifiers [PDF]
مجله مدل سازی در مهندسی, 2019 In this paper, a CMOS operational amplifier (op-amp) for applications requiring a bandwidth several hundreds of MHz will be designed and optimized. The op-amp is two-stage and compensated by current buffer and a Miller capacitor.
Esmaeel Ranjbar +2 more
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IEEE Open Journal of Power Electronics, 2022 Next-generationVariable Speed Drive (VSD) systems utilize SiC MOSFETs to achieve both high efficiency through reduced bridge-leg losses and high power density through an order-of-magnitude increase in switching frequency or reduction of the DC-link ...
Michael Haider +5 more
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Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array [PDF]
IET Circuits, Devices & Systems, 2008 A capacitor-free CMOS low dropout regulator (LDR) using the nested Miller compensation with an active resistor (NMCAR) is presented. It can efficiently control the damping factor and reduce the required Miller compensation capacitance. It can also resolve the trade-off between dc loop gain and damping factor, which existed in the LDR using the nested ...
Huang, W.-J., Liu, S.-I.
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Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach
ETRI Journal, 2023 Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The
Mohammad Ali Bandari +3 more
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IEEE Open Journal of Power Electronics, 2021 The voltage rating of the commercial Gallium Nitride (GaN) power devices are limited to 600/650 V due to the lateral structure. Stacking the low-voltage rating devices is a straightforward approach to block higher dc link voltage. However, the unbalanced
Zhengda Zhang +5 more
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IEEE Open Journal of Power Electronics, 2023 Compared to state-of-the-art IGBTs, SiC power semiconductors allow to achieve ever higher system efficiencies and higher power densities in next-generation Variable Speed Drives (VSDs), thanks to their smaller relative chip size, ohmic on-state ...
Michael Haider +4 more
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Nested Miller compensation capacitor sizing rules for fast-settling amplifier design
Electronics Letters, 2005 The conventional capacitor sizing criterion in nested Miller compensation is aimed at giving a third-order Butterworth response to the amplifier in unity-feedback configuration. However, this approach might not represent the best choice for fast-settling and precise amplifier designs.
Pugliese A +2 more
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Sensors, 2018 High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance.
Zhanghao Yu, Xi Yang, SungWon Chung
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Adaptive Miller capacitor multiplier for compact on-chip PLL filter
Electronics Letters, 2003 An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 µm standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption.
Y. Tang, M. Ismail, S. Bibyk
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