Adaptive Miller capacitor multiplier for compact on-chip PLL filter
Electronics Letters, 2003 An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 µm standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption.
Y. Tang, M. Ismail, S. Bibyk
openaire +2 more sources
Comparison between flying capacitor and modular multilevel inverter [PDF]
, 2009 The paper describes the operational principle of flying capacitor and modular multilevel inverters. The detailed discussions of dc link capacitors voltage balancing methods for both inverters are given in order to enable fair comparison. The causes of dc
Anaya-Lara, O. +5 more
core +3 more sources
Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range
IEEE Access, 2022 This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution ...
Hamed Aminzadeh +2 more
doaj +1 more source
Design of a high stability LDO without off-chip capacitor
Dianzi Jishu Yingyong, 2020 This paper is aimed at researching and designing LDOs without off-chip capacitors. Whether the LDO can stabilize the output voltage when there is no external capacitor is studied. Based on this, a new type of high-stability LDO structure with no off-chip
Huo Dexuan, Zhang Guojun
doaj +1 more source
CMOS low dropout linear regulator with single Miller capacitor [PDF]
Electronics Letters, 2006 A 2–5V 150 mA CMOS low dropout (LDO) linear regulator with a single Miller capacitor of 4pF is presented. The proposed LDO regulator with a bandgap voltage reference has been fabricated in a 0.35 µm CMOS process and the active chip area is 485×586 µm. The maximum output current is 150 mA and the regulated output voltage is 1.8 V.
Huang, W.J., Lu, S.H., Liu, S.I.
openaire +2 more sources
Recycling folded cascode two-stage CMOS amplifier
Memories - Materials, Devices, Circuits and Systems, 2023 In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V.
Ilghar Rezaei +3 more
doaj +1 more source
Extraction of circuit parameters using multi-objective genetic algorithm for design of non-linearly compensated operational amplifiers [PDF]
مجله مدل سازی در مهندسی, 2019 In this paper, a CMOS operational amplifier (op-amp) for applications requiring a bandwidth several hundreds of MHz will be designed and optimized. The op-amp is two-stage and compensated by current buffer and a Miller capacitor.
Esmaeel Ranjbar +2 more
doaj +1 more source
Modified phase-shifted PWM control for flying capacitor multilevel converters [PDF]
, 2007 The issue of voltage imbalance remains a challenge for the flying capacitor multilevel converter. The phase-shifted pulsewidth modulation (PS-PWM) method has a certain degree of self-balancing properties.
Chunmei Feng +5 more
core +2 more sources
An all-inkjet printed flexible capacitor on a textile using a new poly(4-vinylphenol) dielectric ink for wearable applications [PDF]
, 2012 This paper reports a flexible capacitor for wearable applications which has been all-inkjet printed on a standard 65/35 polyester cotton textile using a new poly(4 vinylphenol)(PVP) dielectric material.
Torah, Russel +7 more
core +2 more sources
A FAST TRANSIENT CAPACITOR-LESS LDO REGULATOR WITH ACTIVE FREQUENCY COMPENSATION [PDF]
Proceedings on Engineering SciencesThis paper introduces a low dropout (LDO) regulator designed for system-on-chip applications, operating without an external output capacitor. The design uses a folded cascode amplifier and an active capacitor circuit with a fast comparator to detect the ...
Kunal Keshav , P. Manikandan
doaj +1 more source