Results 211 to 220 of about 28,883 (254)
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Active capacitor multiplier in Miller-compensated circuits
IEEE Journal of Solid-State Circuits, 2000A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads.
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2017 30th IEEE International System-on-Chip Conference (SOCC), 2017 This paper presents a constant bandwidth switched-capacitor programmable-gain amplifier (SC-PGA). By using an adaptive Miller compensation technique for the SC-PGA, our SC-PGA achieves low power consumption and high linearity at various gain conditions.
Hyunjong Kim +3 more
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PSRR Improvement Technique for Amplifiers with Miller Capacitor
2006 IEEE International Symposium on Circuits and Systems, 2006 A simple circuit technique is presented for improving poor midband power supply rejection ratio (PSRR) of single ended amplifiers that use Miller capacitance to set the location of the dominant pole. The principle of the technique is to create an additional parallel signal path from the power supply to the output, which cancels the dominating unity ...
M. Loikkanen, Juha Kostamovaara
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A Super-bandwidth Three-stage Amplifier with Single Miller-capacitor Compensation
2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007 A novel super-bandwidth three-stage amplifier with a new stability method are proposed in this paper. It could produce two left-half-plane zeros to compensate the two non-dominant poles and the dominant pole, which makes the amplifier had very large bandwidth and good phase margin. Moreover, only one Miller capacitor is required, and consumes not large
Yonggen Liu +4 more
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Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers
International Journal of Circuit Theory and Applications, 2007 AbstractA frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor.
S.O. Cannizzaro +3 more
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A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019A transient-enhanced output-capacitor-free low-dropout regulator (LDR) based on dynamic Miller compensation (DMC) is presented in this brief. By utilizing different Miller capacitors to compensate the LDR at different load ranges, the proposed DMC technique can extend the loop bandwidth and enhance the transient performances.
Chenchang Zhan +2 more
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Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2006 This paper proposes a Miller capacitor which has a wide input signal range. By discharging the charge of the capacitor connected between the input and output terminals of an amplifier before the output voltage of the amplifier exceeds its maximum range, the amplifier always operates in the active region and the Miller operation can be guaranteed.
正浩 吉岡, Masahiro Yoshioka
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A Fast Settling Low Dropout Linear Regulator with Single Miller Compensation Capacitor
2005 IEEE Asian Solid-State Circuits Conference, 2005 A 1.8-V, 150-mA fast settling low dropout linear regulator (LDO) with single Miller compensation capacitor is presented. By utilizing the digital-controlled dynamic bias circuit to track the output current, the proposed LDO provides fast settling time for the output capacitors with low and high equivalent series resistance (ESR).
Sao-hung Lu +2 more
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A Capacitor-less LDO with Nested Miller Compensation and Bulk-Driven Techniques in 90nm CMOS
2021 4th International Conference on Circuits, Systems and Simulation (ICCSS), 2021 This paper presents an output-capacitor-less low-dropout regulator (LDO) with nested miller compensation and bulk-driven techniques. The proposed LDO has been fabricated in TSMC 90 nm CMOS technology. The nominal supply voltage of the LDO is 1.8 V and the output voltage is 1.2 V. Bulk-driven technique is used to improve the power supply rejection Ratio
Ruitong Zhang, Zicheng Liu, Xinghua Wang
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Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers
2008 IEEE International Conference on Electron Devices and Solid-State Circuits, 2008 A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced in this work. By utilizing active capacitors to realize the compensation network in a nested way, two inverting gain stages can be used as the second and third gain-stages. The proposed scheme reaches better bandwidth-to-power and slew-rate-to-power
Haifeng Ma +3 more
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