Results 21 to 30 of about 28,883 (254)
A new three-stage amplifier with reduced Miller compensation capacitor utilizing the cascade transformation graph rule [PDF]
M. Ghashghai, M. B. Ghaznavi‐Ghoushchi
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Extraction of circuit parameters using multi-objective genetic algorithm for design of non-linearly compensated operational amplifiers [PDF]
مجله مدل سازی در مهندسی, 2019 In this paper, a CMOS operational amplifier (op-amp) for applications requiring a bandwidth several hundreds of MHz will be designed and optimized. The op-amp is two-stage and compensated by current buffer and a Miller capacitor.
Esmaeel Ranjbar +2 more
doaj +1 more source
A 1.6 Gb/s, 3 mW CMOS receiver for optical communication [PDF]
, 2002 A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and ...
Emami-Neyestanak, Azita +4 more
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Line-start permanent-magnet motor single-phase steady-state performance analysis [PDF]
, 2003 This paper describes an efficient calculating procedure for the steady-state operation of a single-phase line-start capacitor-run permanent-magnet motor.
Cossar, C. +6 more
core +1 more source
Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach
ETRI Journal, 2023 Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The
Mohammad Ali Bandari +3 more
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IEEE Open Journal of Power Electronics, 2021 The voltage rating of the commercial Gallium Nitride (GaN) power devices are limited to 600/650 V due to the lateral structure. Stacking the low-voltage rating devices is a straightforward approach to block higher dc link voltage. However, the unbalanced
Zhengda Zhang +5 more
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Integrated chaos generators [PDF]
, 2002 This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ...
Delgado Restituto, Manuel +1 more
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IEEE Open Journal of Power Electronics, 2023 Compared to state-of-the-art IGBTs, SiC power semiconductors allow to achieve ever higher system efficiencies and higher power densities in next-generation Variable Speed Drives (VSDs), thanks to their smaller relative chip size, ohmic on-state ...
Michael Haider +4 more
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Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS [PDF]
, 2010 This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The
Bos, Lynn +4 more
core +1 more source
Adaptive Miller capacitor multiplier for compact on-chip PLL filter
Electronics Letters, 2003 An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 µm standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption.
Y. Tang, M. Ismail, S. Bibyk
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