Results 281 to 290 of about 4,133,040 (316)
Some of the next articles are maybe not open access.
Multi-core architecture for video decoding
2012 International SoC Design Conference (ISOCC), 2012Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video
Jae-Jin Lee +2 more
openaire +1 more source
An Architecture for Reconfigurable Multi-core Explorations
2011 International Conference on Reconfigurable Computing and FPGAs, 2011Multi-core systems are now the norm, and reconfigurable systems have shown substantial benefits over general purpose ones. This paper presents a combination of the two: a fully featured reconfigurable multi-core processor based on the Leon3 processor.
Olivier Serres +2 more
openaire +1 more source
Resonance, 2017
Multi-core microprocessor is an interconnected set of independent processors called cores integrated on a single silicon chip. These processing cores communicate and cooperate with one another to execute one or more programs faster than a single core processor. In this article we describe how and why these types of processors evolved.
openaire +1 more source
Multi-core microprocessor is an interconnected set of independent processors called cores integrated on a single silicon chip. These processing cores communicate and cooperate with one another to execute one or more programs faster than a single core processor. In this article we describe how and why these types of processors evolved.
openaire +1 more source
IEEE Spectrum, 2010
Designers now accept that although transistors will still get smaller and more numerous on each chip, they aren't going to operate faster than they do toady.And if you tried to incorporate all those transistors into one giant microprocessor, you might well end up with a device that couldn't compute any faster than the chip it was replacing, which ...
openaire +1 more source
Designers now accept that although transistors will still get smaller and more numerous on each chip, they aren't going to operate faster than they do toady.And if you tried to incorporate all those transistors into one giant microprocessor, you might well end up with a device that couldn't compute any faster than the chip it was replacing, which ...
openaire +1 more source
Engineering a Multi-core Radix Sort
2011We present a fast radix sorting algorithm that builds upon a microarchitecture-aware variant of counting sort. Taking advantage of virtual memory and making use of write-combining yields a per-pass throughput corresponding to at least 89% of the system's peak memory bandwidth.
Wassenberg, Jan, Sanders, Peter
openaire +2 more sources
2014
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
openaire +1 more source
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from ...
Mikhail Kovalev +2 more
openaire +1 more source
Multi-core Implementations of Geometric Algorithms
2009This paper presents a framework for multi-core implementations of divide and conquer algorithms and shows its efficiency and ease of use by applying it to some fundamental problems in computational geometry. The framework supports automatic parallelization of any D&C algorithm.
Stefan Näher, Daniel Schmitt 0002
openaire +1 more source
Communication Control for Multi-core Processors
2012 Third International Conference on Digital Manufacturing & Automation, 2012A reconfigurable System-on-Chip (SoC) for multimedia application was introduced in this paper, where the SoC consisted of a master processor and slave processor. We individually simulated the master processor with DLX pipeline processor and the slave processor with Xtensa processor that was able to establish a excellent multimedia processor with multi ...
openaire +1 more source
Multi-core issues---Multi-Core for HPC
Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06, 2006Thomas L. Sterling +6 more
openaire +1 more source
POWER7 multi-core processor design
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009POWER series of processors are the building block for IBM's p-Series servers. With its leading edge microarchitecture, technology and efficient implementation, POWER processors are the dominating RISC processor technology today. POWER processors form the building block for IBM's p-Series servers, which have the largest UNIX marketshare.
openaire +1 more source