Results 21 to 30 of about 36,603 (249)
A case study for NoC based homogeneous MPSoC architectures [PDF]
The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability to next-generation on-chip multiprocessor architectures.
Ruo Roch, Massimo +4 more
core +1 more source
The Noc proteins involved in ribosome synthesis and export contain divergent HEAT repeats [PDF]
The Noc1-4p proteins were previously reported to be involved in intranuclear and nucleocytoplasmic transport of pre-ribosomes. Using fold recognition and structural modeling, we show that Noc1-4p are largely comprised of alpha-helical repeats similar to ...
Tollervey, D, Dlakic, M
core +1 more source
In this paper, we uncover a novel and imminent threat to an emerging computing paradigm: MPSoCs built with 3rd party IP NoCs. We demonstrate that a compromised NoC (C-NoC) can enable a range of security attacks with an accomplice software component. To counteract these threats, we propose Fort-NoCs, a series of techniques that work together to provide ...
Dean Michael Ancajas +2 more
openaire +2 more sources
Preparation and Preliminary Biodistribution Study of 64Cu-NOTA-NOC
The radiolabeling of somatostatin octapeptide analogue NOTA-NOC with 64Cu was carried out. The preliminary study of 64Cu-NOTA-NOC on the in vitro stability, the lipid-water partition coefficient, and the distribution in normal and tumor-bearing mice was ...
ZHAO Hailong;LI Zequang;LUO Tianwei;HUANG Xuhu;WANG Ning;CHEN Mengyi;XU Lin;SHI Xudong;DENG Xuesong;LI Hongyu
doaj +1 more source
Review of Network on Chip Routing Algorithms [PDF]
System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC).
Khurshid Ahmad, Muhammad Sethi
doaj +1 more source
The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs.
Weilong Chen +8 more
doaj +1 more source
Accelerating NoC Verification Using a Complete Model and Active Window
This work presents formal modeling of Network-on-Chip (NoC) considering detailed functional units of NoC. The intricate modeling of NoC router components like buffer, switch, and arbiter is accomplished using Finite State Machine (FSM). As in the case of
Surajit Das +2 more
doaj +1 more source
Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications
The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture is a run-time scalable column-based NoC, where the columns of the NoC
Qaiser Ijaz +3 more
doaj +1 more source
Automated Near Real-Time QC for LC-HRMS. [PDF]
ABSTRACT Rationale The quality of analytical measurements is typically evaluated after completion of the entire, or possibly multiple, measurement batch(es). Automated, near real‐time quality control (QC) during LC‐HRMS acquisition can prevent reruns and sample loss by flagging issues as they occur.
Mohr MJ +6 more
europepmc +2 more sources
Statistical Approach to NoC Design [PDF]
Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability leads network-on-chip (NoC) designers to plan for the worst-case traffic patterns, and ...
Cohen I., Rottenstreich O., Keslassy I.
openaire +3 more sources

