Results 1 to 10 of about 49,281,268 (309)
Discover ElectronicsThis study investigates machine learning (ML) techniques for optimizing Network-on-Chip (NoC) application mapping, focusing on supervised learning, unsupervised learning, reinforcement learning, and neural networks.
Yasin Asadi
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Analisis Unjuk Kerja Flow Control pada Network on Chip dalam Beberapa Kondisi Jaringan
Jurnal Teknik ITS, 2015 Network on Chip ialah teknik yang digunakan di System on Chip sebagai pengganti shared bus dan direct point – to – point. Pada Network on Chip terdapat parameter desain dan parameter performansi jaringan.
Muhammad Hizrian Hizburrahman +2 more
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Dynamic and Static Task Allocation for Hard Real-Time Video Stream Decoding on NoCs [PDF]
Leibniz Transactions on Embedded Systems, 2017 Hard real-time (HRT) video systems require admission control decisions that rely on two factors. Firstly, schedulability analysis of the data-dependent, communicating tasks within the application need to be carried out in order to guarantee timing and ...
Mendis, Hashan R. +2 more
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IEEE AccessNetwork-on-Chip (NoC)-based Spiking Neural Networks (SNNs) provide a scalable platform for neuromorphic computing, but efficient global time-step synchronization remains a critical challenge.
Jingyu Wang, Delong Shang
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Scalable Network-on-Chip Design for FPGA Implementation
IEEE AccessNetwork-on-Chip (NoC) technology has become a fundamental solution to address communication bottlenecks and scalability challenges in modern System-on-Chip (SoC) architectures.
Mekala Bindu Bhargavi +4 more
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Expansible Network-on-Chip Architecture
Advances in Electrical and Computer Engineering, 2018 Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the ...
PIRES, I. L. P. +2 more
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An Approximate Bufferless Network-on-Chip
IEEE Access, 2019 Bufferless network-on-chip (NoC) designs have drawn research attention in massively parallel multicore systems via their significant benefits in power and area savings. However, it shows poor throughput and low bandwidth in current bufferless designs due
Ling Wang, Xiaohang Wang, Yadong Wang
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Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
Journal of Low Power Electronics and Applications, 2017 This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system.
Soundous Chairat +3 more
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A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
IEEE Access, 2016 Wireless communication at near-capacity transmission throughputs is facilitated by employing sophisticated Error Correction Codes (ECCs), such as turbo codes.
Ra'ed Al-Dujaily +5 more
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Routing Algorithms in Networks-on-Chip [PDF]
, 2014 This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are ...
Palesi M., Daneshtalab M.
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