Results 41 to 50 of about 132,420 (284)
A Benchmark Suite of Hardware Trojans for On-Chip Networks
IEEE Access, 2019 As recently studied, network-on-chip (NoC) suffers growing threats from hardware trojans (HTs), leading to performance degradation or information leakage when it provides communication service in many/multi-core systems.
Jian Wang +3 more
doaj +1 more source
IEEE Access, 2021 The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs.
Weilong Chen +8 more
doaj +1 more source
Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures [PDF]
, 2009 This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which ...
Guido Masera +3 more
core +3 more sources
Routing Algorithm Based on Double-layer Network on Chip [PDF]
Jisuanji gongcheng, 2016 This paper presents a fast routing algorithm for the new double-layer Network on Chip(NoC) to make full use of the NoC resources.According to the frequency and total volume of the inter-core communications,the proposed algorithm firstly divides them into
FENG Jie,JING Ming’e,YU Zhiyi
doaj +1 more source
Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs [PDF]
, 2007 Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches.
Christof Teuscher +8 more
core +3 more sources
Network model of on-chip antennas [PDF]
Advances in Radio Science, 2011 A Network model of an ultra-wide band, intra-chip wireless link is presented. Numerical data of Z-parameters, obtained from full wave simulation of the structure, are used to obtain a rational function representation via the Vector Fitting procedure ...
F. Mukhtar, H. Yordanov, P. Russer
doaj +1 more source
Energy-Aware Network-on-Chip Application Mapping Based on Domain Knowledge Genetic Algorithm [PDF]
, 2014 This paper addresses energy-aware application mapping for large-scale Network-on-chip (NoC). The increasing number of intellectual property (IP) cores in multi-processor system-on-chips (MPSoCs) makes NoC application mapping more challenging to find ...
Andromeda, T. (Trias) +4 more
core
Improving Network-on-Chip-based Turbo Decoder Architectures [PDF]
, 2013 In this work novel results concerning Networkon- Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques ...
A Pulimeno +32 more
core +1 more source
Gut microbiome and aging—A dynamic interplay of microbes, metabolites, and the immune system
FEBS Letters, EarlyView.Age‐dependent shifts in microbial communities engender shifts in microbial metabolite profiles. These in turn drive shifts in barrier surface permeability of the gut and brain and induce immune activation. When paired with preexisting age‐related chronic inflammation this increases the risk of neuroinflammation and neurodegenerative diseases.
Aaron Mehl, Eran Blacher
wiley +1 more source
Power-Gating Technique for Network-on-Chip Buffers [PDF]
, 2013 A new approach to reducing leakage power in network-on-chip buffers is presented. The non-uniformity of buffer utilisation is leveraged across the network and power-gating is applied to scarcely utilised buffers.
Bertozzi D. +8 more
core +1 more source