Results 21 to 30 of about 49,281,268 (309)
A Scalable Software Defined Network Orchestrator for Photonic Network on Chips
IEEE Access, 2021 Photonic networks and software-defined networks are two promising technologies to improve network-on-chips performance, scalability, and resource utilization.
Doaa A. Hamdi +3 more
doaj +1 more source
On the capacity of bufferless Networks-on-Chip [PDF]
2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton), 2012 Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs.
Alexander Shpiner +4 more
openaire +1 more source
Technologies, 2020 Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in
Jan Moritz Joseph +4 more
doaj +1 more source
RecoNoC: A reconfigurable network-on-chip [PDF]
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011 This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs.
Robbe Vancayseele +4 more
openaire +2 more sources
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
IEEE Access, 2020 Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is
Waqar Amin +6 more
doaj +1 more source
Congestion-aware wireless network-on-chip for high-speed communication
Automatika, 2020 The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC ...
M. Devanathan +2 more
doaj +1 more source
Congestion aware low power on chip protocols with network on chip with cloud security
Journal of Cloud Computing: Advances, Systems and Applications, 2022 This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors.
Suresh Ponnan +4 more
doaj +1 more source
Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems
IEEE Access, 2021 Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems.
Bichi Bashir Yusuf +3 more
doaj +1 more source
Scalability of Network-on-Chip communication architecture for 3-D meshes. [PDF]
, 2009 Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems.
Awet Yemane Weldezion +25 more
core +1 more source
Design and implementation of the Quarc network on-chip [PDF]
, 2009 Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip.
Moadeli, M. +5 more
core +1 more source