Results 21 to 30 of about 132,420 (284)
Enhanced overloaded code division multiple access for network on chip
IET Computers & Digital Techniques, 2022 The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On
Behnam Vakili, Morteza Gholipour
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A Novel 3D Mesh-Based NoC Architecture for Performance Improvement
Majlesi Journal of Electrical Engineering, 2022 Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption
Navid Habibi +2 more
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Quarc: a high-efficiency network on-chip architecture [PDF]
, 2009 The novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast.
Maji, Partha +2 more
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Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
Моделирование и анализ информационных систем, 2017 In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
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A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips [PDF]
Journal of Artificial Intelligence and Data Mining, 2020 Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links.
A.R. Tajary, E. Tahanian
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Scalability of broadcast performance in wireless network-on-chip [PDF]
, 2016 Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of ...
Abadal Cavallé, Sergi +6 more
core +4 more sources
A global wire planning scheme for Network-on-Chip. [PDF]
, 2003 As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was ...
Liu, J. +3 more
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Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
Journal of Low Power Electronics and Applications, 2017 To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC).
Fernando Gutierrez
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An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC
Sensors, 2021 Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and ...
Saleha Sikandar +5 more
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Low-Power, High-Speed Transceivers for Network-on-Chip Communication [PDF]
, 2009 Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data ...
Klumperink, E.A.M. +4 more
core +3 more sources