Results 21 to 30 of about 124,516 (258)
A Novel 3D Mesh-Based NoC Architecture for Performance Improvement
Majlesi Journal of Electrical Engineering, 2022 Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption
Navid Habibi +2 more
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Proceedings of the 47th Design Automation Conference, 2010 Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential ...
De Micheli G. +5 more
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Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC
IEEE Access, 2020 Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks.
M. Vinodhini, N. S. Murty, T. K. Ramesh
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Enhanced overloaded code division multiple access for network on chip
IET Computers & Digital Techniques, 2022 The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On
Behnam Vakili, Morteza Gholipour
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Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures
IEEE Access, 2023 Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures.
Lashmi Kondoth +3 more
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Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
Моделирование и анализ информационных систем, 2017 In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
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Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
Journal of Low Power Electronics and Applications, 2017 To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC).
Fernando Gutierrez
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An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC
Sensors, 2021 Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and ...
Saleha Sikandar +5 more
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Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach
Micromachines, 2023 Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery.
Zhenmin Li +6 more
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Implementation of NoC on FPGA with Area and Power Optimization [PDF]
EAI Endorsed Transactions on Context-aware Systems and Applications, 2019 On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size,
Momil Ijaz, Huma Urooj, Muhammad Sethi
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