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System-on-Chip: Reuse and Integration [PDF]
Proceedings of the IEEE, 2006 Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called
R Saleh +2 more
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Deep Neural Networks-Based Weight Approximation and Computation Reuse for 2-D Image Classification
IEEE Access, 2022 Deep Neural Networks (DNNs) are computationally and memory intensive, which present a big challenge for hardware, especially for resource-constrained devices such as Internet-of-Things (IoT) nodes.
Mohammed F. Tolba +4 more
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Nanoscale Research Letters, 2022 The adverse effect of ultraviolet (UV) radiation on human beings has sparked intense interest in the development of new sensors to effectively monitor UV and solar exposure.
Ahmed Abusultan +5 more
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DS2B: Dynamic and Secure Substitution Box for Efficient Speech Encryption Engine
IEEE Access, 2021 This paper proposes an efficient encryption technique based on Dynamic and Secure Substitution Box (DS2B) design suitable for IoT and resource-constrained platforms. The DS2B has the advantages of simple structure and good encryption performance.
Mohammed F. Tolba +4 more
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C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal for AI Inference
IEEE Access, 2021 This paper presents a novel cross-coupling capacitor processing unit (C3PU) that supports analog-mixed signal in-memory computing to perform multiply-and-accumulate (MAC) operations.
Dima Kilani +4 more
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Gradient Estimation for Ultra Low Precision POT and Additive POT Quantization
IEEE Access, 2023 Deep learning networks achieve high accuracy for many classification tasks in computer vision and natural language processing. As these models are usually over-parameterized, the computations and memory required are unsuitable for power-constrained ...
Huruy Tesfai +4 more
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System-on-Chip Design and Implementation [PDF]
IEEE Transactions on Education, 2010 The system-on-chip module described here builds on a grounding in digital hardware and system architecture. It is thus appropriate for third-year undergraduate computer science and computer engineering students, for post-graduate students, and as a training opportunity for post-graduate research students.
Linda E. M. Brackenbury +2 more
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Systems-on-Chip with Strong Ordering [PDF]
ACM Transactions on Architecture and Code Optimization, 2021 Sequential consistency (SC) is the most intuitive memory consistency model and the easiest for programmers and hardware designers to reason about. However, the strict memory ordering restrictions imposed by SC make it less attractive from a performance standpoint.
Sooraj Puthoor, Mikko H. Lipasti
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RRAM-based CAM combined with time-domain circuits for hyperdimensional computing
Scientific Reports, 2021 Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient
Yasmin Halawani +5 more
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Hyper-Dimensional Computing Challenges and Opportunities for AI Applications
IEEE Access, 2022 Brain-inspired architectures are gaining increased attention, especially for edge devices to perform cognitive tasks utilizing its limited energy budget and computing resources.
Eman Hassan +3 more
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