A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications [PDF]
This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient
Yunfeng Hu +6 more
doaj +2 more sources
Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications [PDF]
A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a ...
Hsuan-Lun Kuo, Shih-Lun Chen
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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
doaj +3 more sources
Exploiting Smallest Error to Calibrate Non-Linearity in SAR Adcs [PDF]
This paper presents a statistics-optimized organization technique to achieve better element matching in successive approximation register (SAR) analog-to-digital converter (ADC) in smart sensor systems.
Hua Fan +7 more
doaj +3 more sources
A Low-Power, Auto-DC-Suppressed Photoplethysmography Readout System with Differential Current Mirrors and Wide Common-Mode Input Range Successive Approximation Register Analog-to-Digital Converter [PDF]
This paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently ...
Chanyoung Son +2 more
doaj +2 more sources
A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation [PDF]
A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC ...
Yunfeng Hu +8 more
doaj +2 more sources
With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts.
Chih-Hsuan Lin, Kuei-Ann Wen
doaj +1 more source
This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit ...
Dong Suk Kang, Shimeng Yu
doaj +1 more source
This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate
Sang-Hun Lee, Won-Young Lee
doaj +1 more source
Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC
The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-
Harsh Sawardekar, Jayamala Adsul
openaire +1 more source

