A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications [PDF]
Micromachines, 2022 This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient
Yunfeng Hu +6 more
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Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications [PDF]
MicromachinesA 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a ...
Hsuan-Lun Kuo, Shih-Lun Chen
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A Low-Power, Auto-DC-Suppressed Photoplethysmography Readout System with Differential Current Mirrors and Wide Common-Mode Input Range Successive Approximation Register Analog-to-Digital Converter [PDF]
MicromachinesThis paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently ...
Chanyoung Son +2 more
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Electronics Letters, 2019 A dither‐based background calibration with data‐weighted averaging logic to correct capacitor mismatch and inter‐stage gain error in pipelined noise shaping successive approximation register ADCs is proposed.
Peng Wang, Jie Sun, Jianhui Wu
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A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation [PDF]
SensorsA 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC ...
Yunfeng Hu +8 more
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Background bit‐weight calibration in pipelined successive approximation register ADC
Electronics Letters, 2020 A background bit‐weight calibration in pipelined successive approximation register ADC is proposed. By exploiting the conversion results of the first stage to determine the injection of the dithered signal and introducing two extra capacitors into the first stage to reduce the range of first‐stage residue, a robust and totally background calibration is
exaly +2 more sources
Journal of Low Power Electronics and ApplicationsA power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating ...
Xinyuan He +3 more
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Journal of Low Power Electronics and Applications, 2021 With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts.
Chih-Hsuan Lin, Kuei-Ann Wen
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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022 This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit ...
Dong Suk Kang, Shimeng Yu
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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
Active and Passive Electronic Components, 2023 This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
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