Results 21 to 30 of about 2,393 (257)
Sensors, 2015 This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling
Min-Kyu Kim +2 more
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Energy‐efficient switching method for SAR ADCs with bottom plate sampling
Electronics Letters, 2016 A high energy‐efficiency capacitor switching scheme for successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. The switching method, verified on a 10‐bit SAR scheme that uses bottom plate sampling, achieves an average
Yulin Zhang +2 more
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A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET
IEEE Access, 2021 This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng +3 more
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Electronics Letters, 2023 This letter proposes a reconfigurable bandpass noise‐shaping successive approximation register analog‐to‐digital converter (ADC) with a cascade of integrators with feedforward (CIFF) structure.
Jonghyun Kim, Younggyun Oh, Hyungil Chae
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An expandable 36‐channel neural recording ASIC with modular digital pixel design technique
Electronics Letters, 2023 This paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has
Quan Wang +8 more
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Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors
MATEC Web of Conferences, 2016 This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit ...
Aziza Sassi Ben, Dzahini Daniel
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Meta‐stability immunity technique for high speed SAR ADCs
Electronics Letters, 2017 An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre ...
L. Qiu, K. Tang, Y.J. Zheng, L. Siek
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Sensors, 2018 Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques.
Jae-Hun Lee +5 more
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Electronics Letters, 2023 This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee +9 more
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Implementation of a digital trim scheme for SAR ADCs [PDF]
Advances in Radio Science, 2013 Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
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