Results 21 to 30 of about 48,643 (286)
Power Efficient Successive Approximation Registers
IOSR journal of VLSI and Signal Processing, 2014 In recent years, there has been a growing need for Successive Approximation Register (SAR) Analogto-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs.
I.Hitha Chowdary, G.Anitha Chowdary
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A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs
IEEE Access, 2020 A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper.
Lei Qiu +3 more
doaj +1 more source
High Linearity SAR ADC for Smart Sensor Applications [PDF]
, 2018 This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor ...
Cen, Yuanjun +7 more
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Direct Application of the Phase Estimation Algorithm to Find the Eigenvalues of the Hamiltonians [PDF]
, 2008 The eigenvalue of a Hamiltonian, $\mathcal{H}$, can be estimated through the phase estimation algorithm given the matrix exponential of the Hamiltonian, $exp(-i\mathcal{H})$.
de Sene, Renata Karina +6 more
core +5 more sources
Nonredundant successive approximation register forA/D converters
Electronics Letters, 1996 A successive approximation register for N bit A/D converters is presented. It code the possible 2/sup N/ conversion output values with the minimum number FF (log/sub N/). As it is nonredundant and very simple, it allows area optimisation and minor code probability error.
A. Rossi, G. Fucili
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A Novel Biphasic-Current-Pulse Calibration Technique for Electrical Neural Stimulation [PDF]
, 2014 One of the major challenge in neural prosthetic device design is to ensure charge-balanced stimulation. This paper presents a new calibration technique to minimize the mismatch between anodic and cathodic current amplitudes.
Ren, MH, Wang, L, Wang, ZY, Zhang, J
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A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration
IEEE Access, 2023 This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC. The proposed method sequentially corrects capacitor mismatch from the lower to the upper bits in the CDAC.
Sunghyun Bae +5 more
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PixFEL: development of an X-ray diffraction imager for future FEL applications [PDF]
, 2017 A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm.
Battignani, Giovanni +21 more
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The Journal of Engineering, 2014 This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs) of successive approximation register analog-to-digital converter (ADC).
Lei Sun, Kong-Pang Pun, Wai-Tung Ng
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IET Circuits, Devices and Systems, 2022 In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch.
Hamid Mahmoodian +3 more
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