Results 41 to 50 of about 48,643 (286)
A low-power reconfigurable ADC for biomedical sensor interfaces [PDF]
This paper presents a 12-bit low-voltage low-power reconfigurable Analog-to-Digital Converter (ADC). The design employs Switched Capacitor (SC) techniques and implements a Successive Approximation (SA) algorithm.
Delgado Restituto, Manuel +3 more
core +1 more source
Meta‐stability immunity technique for high speed SAR ADCs
An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre ...
L. Qiu, K. Tang, Y.J. Zheng, L. Siek
doaj +1 more source
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be ...
Behnam Samadpoor Rikan +9 more
doaj +1 more source
Implementation of a digital trim scheme for SAR ADCs [PDF]
Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
doaj +1 more source
Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques.
Jae-Hun Lee +5 more
doaj +1 more source
ABSTRACT Background and Aims Wilms tumour (WT) has excellent event‐free and overall survival (OS). However, small differences exist between countries participating in the same international study. This led us to examine variation in adherence to protocol recommendations as a potential contributing factor.
Suzanne Tugnait +23 more
wiley +1 more source
The authors present a dither‐less background digital bit weights calibration method for split‐capacitor digital‐to‐analog converter (CDAC) successive approximation register (SAR) analog‐to‐digital converters (ADCs) to improve non‐linearities caused by ...
Soohoon Lee, Jintae Kim
doaj +1 more source
Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10
ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA +2 more
doaj +1 more source
Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods
This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles ...
Reza Inanlou +2 more
doaj +1 more source
ABSTRACT Purpose Pediatric central nervous system (CNS) tumors often recur despite multimodality therapy. Although re‐irradiation (re‐RT) has historically been limited by concerns for severe late toxicities, modern techniques have renewed interest in this approach. Proton therapy provides dosimetric advantages that may enable curative re‐treatment with
Jin‐Ho Song +15 more
wiley +1 more source

