Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
doaj +3 more sources
A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction [PDF]
This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate
Sang-Hun Lee, Won-Young Lee
doaj +2 more sources
A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications [PDF]
This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient
Yunfeng Hu +6 more
doaj +2 more sources
A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications [PDF]
A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are
Kawther I. Arafa +4 more
doaj +2 more sources
A Phase-Adjustable Noise-Shaping SAR ADC for Mitigating Parasitic Capacitance Effects from PIP Capacitors [PDF]
High parasitic capacitance from poly-insulator-poly capacitors in complementary metal oxide semiconductor (CMOS) processes presents a major bottleneck to achieving high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs)
Xuelong Ouyang +4 more
doaj +2 more sources
Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC
The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-
Harsh Sawardekar, Jayamala Adsul
openaire +1 more source
Low-Power SAR ADCs: Basic Techniques and Trends
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to ...
Pieter Harpe
doaj +1 more source
Low-Power Switching Scheme with Quarter Reference Voltage Sources for SAR ADCs [PDF]
In this paper, an energy-efficient switching scheme with additional quarter-reference voltage sources in a successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for a low power and small area device for frequency modulated
Hyun-Yeop Lee +7 more
doaj +1 more source
Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10
ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA +2 more
doaj +1 more source
The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input
Xingshuai Zou, Jiaxin Liu, Qiang Li
doaj +1 more source

