Results 31 to 40 of about 1,417 (268)
An expandable 36‐channel neural recording ASIC with modular digital pixel design technique
Electronics Letters, 2023 This paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has
Quan Wang +8 more
doaj +1 more source
A 12-bit, 10 Msps two stage SAR-based pipeline ADC [PDF]
, 2013 textThe market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required
Gandara, Miguel Francisco
core
Annals of Clinical and Translational Neurology, EarlyView.Epigenetic reprogramming in hematopoietic stem and progenitor cells (HSPCs) and downstream myeloid cells, mediated by H3.3 downregulation and endogenous retroelement (ERE) overexpression, contributes to the progression of multiple sclerosis (MS). ABSTRACT Background Skewed myelopoiesis in the bone marrow has been identified as a key driver of multiple ...
Li‐Mei Xiao +6 more
wiley +1 more source
Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
ChipsThe noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs.
Zhaoyang Shen, Shiheng Yang, Jiaxin Liu
doaj +1 more source
Electronics Letters, 2019 A resolution‐reconfigurable, bandwidth‐scalable analogue‐to‐digital converter (ADC) with programmable‐gain (PG) functionality for a multi‐sensor system, which encompasses various signals such as bio‐signals and battery‐level, is presented.
J. Rhee, S. Kim
doaj +1 more source
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS
IEEE Access, 2021 This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems.
Manxin Li +7 more
doaj +1 more source
Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA
, 2012 Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor ...
P. Torkzadeh +2 more
core +1 more source
Arthritis Care &Research, EarlyView.Objective Several case reports have proposed a potential association between COVID‐19 vaccination and the subsequent development of idiopathic inflammatory myositis (IIM). This study examined prior COVID‐19 vaccination in US veterans who developed new‐onset IIM compared to those without new‐onset IIM.
Caleb Hernández +10 more
wiley +1 more source
Advanced Healthcare Materials, EarlyView.A multivalent DNA nanostructure‐enabled lateral flow assay was developed for rapid, ultrasensitive detection of porcine epidemic diarrhea virus (PEDV) nucleocapsid protein. Designer net‐shaped DNA nanostructures (DNA‐Net) presenting PEDV‐specific aptamers achieved ~1000‐fold enhanced binding, enabling detection of viral copies with Ct ≤ 37.42 within 10
Saurabh Umrao +9 more
wiley +1 more source
A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications
IEEE Access, 2019 This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution ...
Byungjoo Oh +2 more
doaj +1 more source