Results 11 to 20 of about 1,417 (268)
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022 This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit ...
Dong Suk Kang, Shimeng Yu
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A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET
IEEE Access, 2021 This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng +3 more
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Implementation of a digital trim scheme for SAR ADCs [PDF]
Advances in Radio Science, 2013 Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
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Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
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Electronics Letters, 2022 Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications.
Weihao Wang +3 more
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IEEE Access, 2023 This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over
Hyeonsik Kim, Soohoon Lee, Jintae Kim
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A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]
Journal of Electrical and Computer Engineering Innovations, 2017 A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
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Two‐step, piecewise‐linear SAR ADC with programmable transfer function
Electronics Letters, 2019 A 7‐bit successive approximation register (SAR) analogue‐to‐digital converter (ADC) with programmable transfer functions is presented. Building upon prior art, a two‐step successive approximation technique is used to implement a piecewise‐linear ...
S. Sengupta, M.L. Johnston
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Energy‐efficient switching method for SAR ADCs with bottom plate sampling
Electronics Letters, 2016 A high energy‐efficiency capacitor switching scheme for successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. The switching method, verified on a 10‐bit SAR scheme that uses bottom plate sampling, achieves an average
Yulin Zhang +2 more
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IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
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