Results 21 to 30 of about 1,417 (268)
Radiation-hardened successive approximation register analog-to-digital converter
, 2020 Radiation-hardened-by-design (RHBD) techniques have kept evolving for the past decades to satisfy the requirements of irradiating environments; however, the possibilities of severe nuclear accidents still remain.
Inyong Kwon +11 more
core +1 more source
A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning
IEEE Access, 2019 This paper presents a high-precision biomedical sensor system with a novel analog-frontend (AFE) IC and error correction by machine learning. The AFE IC embeds an analog-to-digital converter (ADC) architecture called successive stochastic approximation ...
Yusaku Hirai +6 more
doaj +1 more source
100 MS/s, 10-bit ADC using pipelined successive approximation [PDF]
, 2014 This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages.
Hadidi, Kheyrollah +4 more
core +1 more source
Meta‐stability immunity technique for high speed SAR ADCs
Electronics Letters, 2017 An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre ...
L. Qiu, K. Tang, Y.J. Zheng, L. Siek
doaj +1 more source
Sensors, 2018 This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique,
Yongkui Yang +3 more
doaj +1 more source
Electronics Letters, 2023 This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee +9 more
doaj +1 more source
IEEE Access, 2021 A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed.
Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
doaj +1 more source
A Review on Fundamentals of Noise-Shaping SAR ADCs and Design Considerations
ChipsA general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR).
Victor H. Arzate-Palma +3 more
doaj +1 more source
A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs
IEEE Access, 2020 A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper.
Lei Qiu +3 more
doaj +1 more source
FEBS Open Bio, EarlyView.Time‐restricted feeding (TRF) in mice increased liver fatty acid oxidation and decreased fatty acid biosynthesis. These alterations persisted when TRF was discontinued and the host was infected with Mycobacterium tuberculosis. Pre‐exposure to TRF did not alter tissue (lung and spleen) mycobacterial burden but significantly reduced CD3+ T cells in lungs
Ashish Gupta +7 more
wiley +1 more source