Results 11 to 20 of about 48,643 (286)
Electronics Letters, 2019 A dither‐based background calibration with data‐weighted averaging logic to correct capacitor mismatch and inter‐stage gain error in pipelined noise shaping successive approximation register ADCs is proposed.
Peng Wang, Jie Sun, Jianhui Wu
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Background bit‐weight calibration in pipelined successive approximation register ADC
Electronics Letters, 2020 A background bit‐weight calibration in pipelined successive approximation register ADC is proposed. By exploiting the conversion results of the first stage to determine the injection of the dithered signal and introducing two extra capacitors into the first stage to reduce the range of first‐stage residue, a robust and totally background calibration is
openaire +3 more sources
Digital‐domain dual‐calibration for single‐ended successive approximation register ADCs
Electronics Letters, 2015 A digital‐domain dual‐calibration for single‐ended successive approximation register analogue‐to‐digital converters (SAR ADCs) is presented. The dual‐calibration combines digital error correction with capacitor mismatch calibration to compensate the decision errors and improve capacitor matching. Simulation results show that the proposed digital‐domain
Zhilun Lin, Jianhui Wu, Chao Chen
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Two CMOS time to digital converters using successive approximation register logic
IEICE Electronics Express, 2018 Himchan Park +5 more
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Applied Sciences, 2023 In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices,
Yunfeng Hu +8 more
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Electronics Letters, 2023 The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input
Xingshuai Zou, Jiaxin Liu, Qiang Li
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A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology [PDF]
MATEC Web of ConferencesThis research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits.
Lakshmi Bhavani G. +6 more
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Low-Power SAR ADCs: Basic Techniques and Trends
IEEE Open Journal of the Solid-State Circuits Society, 2022 With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to ...
Pieter Harpe
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High-Resolution ADCs Design in Image Sensors [PDF]
, 2018 This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and ...
Cen, Yuanjun +7 more
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Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC [PDF]
, 2017 This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application.
Cen, Yuanjun +5 more
core +1 more source