Results 11 to 20 of about 2,393 (257)
In recent years, due to the rise of the Internet of Things (IoT), various sensors have come to be in great demand for IoT devices. Analog-to-digital converters (ADCs) act as an important part of receivers in sensors. To improve the uptime of IoT devices,
Yunfeng Hu +8 more
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The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input
Xingshuai Zou, Jiaxin Liu, Qiang Li
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A 1.2v ΔΣ ADC Modulator Using 4-bit SAR Quantizer for Biomedical Applications by using 65nm CMOS Technology [PDF]
This research focuses on enhancing Sigma-Delta ADC modulators for biomedical applications by leveraging the working principle of Successive Approximation ADC circuits.
Lakshmi Bhavani G. +6 more
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A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs
A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper.
Lei Qiu +3 more
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Low-Power SAR ADCs: Basic Techniques and Trends
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to ...
Pieter Harpe
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Power Efficient Successive Approximation Registers
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analogto-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs.
I.Hitha Chowdary, G.Anitha Chowdary
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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch.
Hamid Mahmoodian +3 more
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A 13-Bit 1-MS/s SAR ADC With Completion-Aware Background Capacitor Mismatch Calibration
This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC. The proposed method sequentially corrects capacitor mismatch from the lower to the upper bits in the CDAC.
Sunghyun Bae +5 more
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This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs) of successive approximation register analog-to-digital converter (ADC).
Lei Sun, Kong-Pang Pun, Wai-Tung Ng
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Two‐step, piecewise‐linear SAR ADC with programmable transfer function
A 7‐bit successive approximation register (SAR) analogue‐to‐digital converter (ADC) with programmable transfer functions is presented. Building upon prior art, a two‐step successive approximation technique is used to implement a piecewise‐linear ...
S. Sengupta, M.L. Johnston
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